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參數(shù)資料
| 型號： | PSD211RL |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設(shè)備 |
| 文件頁數(shù)： | 16/51頁 |
| 文件大?。?/td> | 348K |
| 代理商： | PSD211RL |
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13
PSD211R
10.0
I/OPort
Functions
(Cont.)
10.2 Port A (PA0-PA7)
(Cont.)
Latched Address Output Mode
Alternatively, any bit(s) of Port A can be configured to output a low-order demultiplexed
address bus bit. The address is provided by the internal PSD address latch, which latches
the address on the trailing edge of ALE/AS. Port A then outputs the desired demultiplexed
address bits. This feature can eliminate the need for an external latch (for example:
74LS373) if you have devices that require low-order latched address bits. Although any pin
of Port A may output an address signal, the pin is position-dependent. In other words, pin
PA0 of Port A may only pass A0, PA1 only A1, and so on.
The control registers of Port A are located in CSIOPORT space; see Table 5. Each pin of
Port A can be individually configured. The following table summarizes what the control
registers (in CSIOPORT space) for Port A do:
NOTE:
1. Default value is the value after reset.
Default
Value
(Note 1)
Register Name
0 Value
1 Value
Port A Pin Register
Sampled logic level
at pin = ‘0’
Pin is configured
as input
Data in DFF = ‘0’
Sampled logic level
at pin = ‘1’
Pin is configured
as output
Data in DFF = ‘1’
X
Port A Direction Register
0
Port A Data Register
0
Figure 5. Port A Pin Structure
READ PIN
PORT A PIN
ENABLE
LATCHED
ADDR
OUT
MCU
I/O
OUT
READ DATA
WRITE DATA
ALE
READ DIR
WRITE DIR
RESET
CK
D
R
G
D
R
D
CK
R
I
N
T
E
R
N
A
L
A
D
D
R
/
D
A
T
A
B
U
S
A
D
0
/
A
D
7
DFF
LATCH
DIR
FF
CONTROL
MUX
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PSD211RM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
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| PSD2-120 | 制造商:Tamura Corporation of America 功能描述: |
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| PSD2-20 | 制造商:Tamura Corporation of America 功能描述: |
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