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參數(shù)資料
| 型號： | PS21204 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | TRANSFER-MOLD TYPE INSULATED TYPE |
| 中文描述： | 轉(zhuǎn)讓模具類型絕緣型 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大小： | 187K |
| 代理商： | PS21204 |
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21204
TRANSFER-MOLD TYPE
INSULATED TYPE
Aug. 1999
Fig. 8 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
Note 1:
To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short
as possible. (Less than 2cm)
2:
By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler
or transformer isolation is possible.
3:
F
O
output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately
5.1k
resistance.
4:
F
O
output pulse width should be decided by connecting an external capacitor between CFO and V
NC
terminals (C
FO
). (Example : C
FO
= 22 nF
→
t
FO
= 1.8 ms (typ.))
5:
Each input signal line should be pulled up to the 5V power supply with approximately 4.7k
resistance (other RC coupling circuits at
each input may be needed depending on the PWM control scheme used and on the wiring impedances of the system’s printed circuit
board). Approximately a 0.22~2
μ
F by-pass capacitor should be used across each power supply connection terminals.
6:
To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
7:
In the recommended protection circuit, please select the R
1
C
5
time constant in the range 1.5~2
μ
s.
8:
Each capacitor should be put as nearby the pins of the DIP-IPM as possible.
9:
To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approxi-
mately a 0.1~0.22
μ
F snubber capacitor between the P&N1 pins is recommended.
HO
HO
DIP-IPM
C1: Tight to lerance temp-compensated electrolytic type; C2,C3: 0.22~2
F R-category ceramic capacitor for noise filtering
(Note : The capacitance value depends on the PWM control used in the applied system)
C3
C3
C3
C3
C2
C2
C2
C1
C1
C1
HO
IN
IN
15V line
5V line
5V line
IN
COM
COM
COM
U
OUT
V
OUT
W
OUT
V
NO
CFO
GND
F
o
W
N
V
N
V
CC
C
B
A
C4(C
FO
)
CFO
R1
C5
Shunt
Resistor
CIN
CIN
N1
N
W
V
U
P
V
S
V
S
V
S
V
B
V
B
V
B
V
CC
V
CC
V
CC
Fo
W
N
V
N
U
N
U
N
W
P
V
P
U
P
V
NC
V
N1
V
PC
V
P1
V
P1
V
P1
V
WFS
V
VFS
V
UFS
V
WFB
V
VFB
V
UFB
M
R
Sh
For detailed description of the boot-strap circuit
construction, please contact Mitsubishi Electric
C
P
U
U
N
I
T
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