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參數(shù)資料
| 型號(hào)： | PRODUCT |
| 英文描述： | Product Selection Guide 2002 |
| 中文描述： | 產(chǎn)品選型指南2002 |
| 文件頁(yè)數(shù)： | 18/26頁(yè) |
| 文件大小： | 1061K |
| 代理商： | PRODUCT |
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15
L84720
MDC
MDIO
TxA+
TxA-
RxA+
RxA-
Lane A
Lanes BthruD
Management Interface
TopLevel Contros
RFC
REF CLK
JTAGSignals
MODE [3:0]
RxC
RFC
RFC
RDA[4:0]
TxC
TDA[4:0]
Smoothng
FIFO
Tx
Buffer
BIST
JTAG
Rx
Buffer
Rx Cock
Generator
Deserializer
GgaBaze Receiver
GgaBaze Transmtter
Tx Cock
Generator
Serializer
Four complete Serializers/ Deserializers
(SerDes)
Low noise: Terminations integrated
into SerDes cores
Flexible Serial data rates: 1.0 to 1.6
Gbps
Compliant to or Supporting the
following Standards:
- Gigabit Ethernet (1.25 Gb/ s
data rate)
- Fiber Channel Data Rates as
a SerDes
Reduced Ten Bit Interface (RTBI)
- Pin Saving DDR Interface
Management Interface
- MDC/ MDIO (IEEE 802.3ae,
Clause 45)
- Pin Strapping options for
non-managed designs
Equalization: Emphasis
Direct connection to VECSEL other
Optical Modules (non-W DM) through
Signal Detection Pin
- Hot pluggable Serial I/ O
- RxLoss Signal
Test Mode Support
- Built-in Self Test (BIST)
- Internal serial loopbacks
- JTAG Boundary Scan Support
- PRBS
Low power consumption
- <1.2 W typical @ 1.25 Gbps
(<400 mW per channel)
Two Power Supplies
- 1.8v core
- 2.5v I/ 0
289-ball PBGA Package
(19 X 19mm)
L84720
4-Port Ggabt Ethernet SerDes
L84720 Block Diagram
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