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參數(shù)資料
| 型號： | PRISM1RC |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 112K |
| 代理商： | PRISM1RC |
4-383
TXDATA (I) Pin 28
This pin is used to transfer serial data or preamble/header
data from a MAC or network processor to the baseband
processor. The LSB is received first and the data is clocked
in the baseband processor at the falling edge of TXC. A data
bit high = “one”.
TXC (O) Pin 33
Output clock signal to the MAC or network processor used to
input serial data to the baseband processor. The data is
clocked into the baseband processor using the falling edge
of TXC.
TX_RDY (O) Pin 67
Output to the MAC or network processor which indicates that
the preamble or header has been generated. This signals
that the baseband processor is ready to receive serial data
for transmitting over the TXDATA serial line from the MAC or
network processor.
TX_RDY signal returns to the inactive state when the PA_PE
indicating end of transmission.
CCA (O) Pin 62
Clear Channel Assessment signal indicates the availability of
the channel for transmission. The CCA algorithm is user
programmable. The detailed operation of this pin may be
found in the PRISM Baseband Processor data sheet [5]. The
active level of this signal is programmable.
RXDATA (O) Pin 63
Output to a MAC or a network processor which transfers
demodulated header information and data in serial format.
The LSB is sent first and is aligned with the MD_RDY signal
(see Figure 7).
RXCIN (O) Pin 36
This clock signal is used to serially transfer the header and
data from the RXDATA pin to the MAC or network processor.
The signal is held low when not transferring data.
MD_RDY (O) Pin 59
Signal to a MAC or network processor indicating a data
packet is ready. The signal envelopes the data transfer over
the RXD serial line.
RX_PE_BB (I) Pin 12
When set high the baseband processor is in receive mode.
SD/SYNTH_DATA (I/O) Pin 30
There are two purposes for this pin. In regards to the
baseband processor, this serial line is used to transfer
address and data to and from the baseband processor. The
MSB is always transferred first. In regards to the synthesizer,
the address and data are programmed through this line. The
MSB is always first (see Figures 3 and 4).
CLK/SYNTH_CLK (I) Pin 20
This signal is used for serial bus transfers to program the
baseband processor and the synthesizer. The data is clocked
on the rising edge of the signal at a maximum rate of 10MHz.
Even though, CLK/SYNTH_CLK are low frequency, rise and
fall times of less than 10ns should be observed.
BB_AS (I) Pin 13
Address strobe is used to envelope the address or the data
on SD/SYNTH_DATA while programming the baseband
processor. When high, it envelops the address bits. When
low, it envelops the data bits (see Figures 2 and 3).
BB_RD/WR (I) Pin 19
Used to change the direction of the SD/SYNTH_DATA line
while programming the baseband processor. This signal
must be set up prior to the rising edge of CLK/SYNTH_CLK.
BB_CS (I) Pin 14
Active low signal. Baseband processor Chip select signal.
When inactive, the signals BB_AS and BB_RD/WR become
don’t cares.
RESET_BB (I) Pin 26
Active low signal. Baseband processor reset. Must be
inactive during programming. When active RX and TX
functions are disabled (see Figure 5).
RADIO_PE (I) Pin 24
This signal, when asserted high, enables the radio card.
Power is applied to all chips.
This signal should be kept high during operation of this card.
SEL0 (I) and SEL1 (I) Pins 22, 23
Select the cutoff frequency for the low pass filters in HFA3724
used before going into the Modulator/Demodulator circuit.
SEL1
LO
LO
HI
SEL0
LO
HI
LO
Cutoff Frequency
2.2MHz
4.4MHz
8.8MHz <-- used for 2 Mbps DQPSK,
11 chips
17.6MHz
HI
HI
TX_PE (I) Pin 29
This signal, when asserted high, enables the transmit
section of the Modulator/Demodulator and RF/IF Up/Down
converter circuits.
RX_PE (I) Pin 27
This signal, when asserted high, enables the receiver
section of the Modulator/Demodulator and RF/IF Up/Down
converter circuits.
SYNTH_LE (I) Pin 21
SYNTH_LE, CLK/SYNTH_CLK and SD/SYNTH_DATA
signals are used to program the synthesizer. SYNTH_LE
latches a frame of 22 bits after it has been shifted by the
CLK/SYNTH_CLK into the synthesizer registers. Please
note that the clock and data lines are shared also by the
baseband processor.
Application Note 9808
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| PRIXP420BB | 功能描述:IC NETWRK PROCESSR 266MHZ 492BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| PRIXP420BC | 功能描述:IC NETWRK PROCESSR 400MHZ 492BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| PRIXP420BD | 功能描述:IC NETWRK PROCESSR 533MHZ 492BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
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