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參數資料
| 型號： | PRISM1KIT-EVAL |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數： | 4/21頁 |
| 文件大?。?/td> | 140K |
| 代理商： | PRISM1KIT-EVAL |
4
The gain distribution/limiter noise analysis is shown in
Appendix F. If the alternative HFA3624 broadband matching
network is used, the HFA3624 mixer conversion gain will be
higher, which will help ensure that the second limiter is fully
limited on front-end noise.
At the output of the limiters, a 200mV
P-P
differential signal level
is maintained under all input conditions. This limited signal is
then mixed in quadrature to baseband in the HFA3724
Quadrature IF Modulator/Demodulator. The LO needed for the
quadrature mixing is applied at twice the IF frequency, or
560MHz. A divide by two circuit then provides an accurate
quadrature LO for the mixers. The baseband outputs of the
quadrature mixers areACcoupled off-chip tothe integrated fifth
order Butterworth filters. The output levels of the low pass filters
are nominally 500mV
P-P
single-ended, and are intended to be
AC coupled to the HFA3824A Baseband Processor. The AC
coupling time constant is approximately 25 times longer than
the symbol period, and is implemented with 0.01
μ
F series
capacitors. These coupling capacitors must be taken into
account, however, when estimating the time it takes to power
up or awaken from sleep mode.
At the input to the HFA3824A Baseband Processor, the
quadrature signals are analog to digital converted in
wideband 3 bit converters. The sample rate is 22MSPS,
which results in two samples per chip. A 22MHz Fox F4106
crystal oscillator is used to provide the main clock for the
HFA3824A. The signals are spread spectrum with no DC
term, so it is feasible to AC couple the signals to the ADCs
and avoid DC bias offsets. The signal at this point has been
limited to a constant IF amplitude and then passed through
two separate mixer and low pass filter paths. The component
variations in these two paths can introduce offsets in
amplitude and phase and can also use up some of the
headroom in the ADCs. The maximum amplitude variation is
2dB and the maximum phase balance variation is 4 degrees.
Since the signal is limited, the IF signals will have low peak
to average ratios even with noise as an input. The I and Q
signals will have sinusoidal properties with PSK modulation
imposed. It is their combined vector magnitude that is
limited, not their individual amplitudes. To optimize the
demodulator’s performance, the ADCs are operated at the
point where they are at full scale on either I or Q one third of
the time. To maintain this operating point in the face of
component variations, there is an optional active adjustment
of the ADC reference voltage by feedback. This avoids the
necessity of allowing extra headroom for the variation. The
adjustment circuit is very slow and averages the energy from
the two channels over both packet and noise conditions.
The HFA3824A Baseband Processor correlates the PN
spreading to remove it and to uncover the differential BPSK
or QPSK data. The processor initially uses differential
detection to identify and lock onto the signal. It then makes
measurements of the carrier and symbol timing phase and
frequency and uses these to initialize tracking loops for fast
acquisition. Once demodulating and tracking, the processor
uses coherent demodulation for best performance. Since
this radio uses a spread spectrum signal with 10.4dB of
processing gain (10 log 11), the signal to noise ratio (SNR)
in the chip rate bandwidth is approximately 0dB when the
demodulator is at the desired bit error rate in BPSK. The
radio operates with about 2.5dB of implementation loss
relative to theoretical performance and achieves a sensitivity
of -91dBm in the BPSK mode of operation.
The HFA3824A Baseband Processor provides differential
decoding and descrambling of the data to prepare it for the
Media Access Controller (MAC). The MAC is an AMD
AM79C930 PCnet - Mobile controller. All packet signals have
a preamble followed by a header containing a start frame
delimiter (SFD), other signal related data and a cyclic
redundancy check (CRC). The MAC processes the header
data to locate the SFD, determine the mode and length of
the incoming message and to check the CRC. The MAC
then processes the packet data and sends it on through the
PC Card interface to the host computer. The MAC checks
the packet data CRC to determine the data purity. If
corrupted data is received, a retransmission is requested by
the MAC which handles the physical layer link protocols.
Transmit Processing
Data from the host computer is sent to the MAC via the PC
Card interface. Prior to any communications, however, the
MAC sends a Request to Send (RTS) packet to the other
end of the link and receives a Clear to Send (CTS) packet.
The MAC then formats the payload data packet (MPDU) by
appending it to a preamble and header and sends it on to the
HFA3824A Baseband Processor which clocks it in. The
HFA3824A Baseband Processor scrambles the packet and
differentially encodes it before applying the spread spectrum
modulation. The data can be either DBPSK or DQPSK
modulated at 1MSPS and is a baseband quadrature signal
with I and Q components. The BPSK spreading is an 11 chip
Barker sequence that is clocked at 11MHz and is modulated
with the I and Q data components. These are then output to
the HFA3724 as CMOS logic signals. Following the
RTS/CTS/MPDU is an acknowledge (ACK) packet by the
receiving side of the link.
Transmit quadrature single-bit digital inputs are applied to the
HFA3724 Quadrature IF Modulator/Demodulator from the
HFA3824A Baseband Processor. These inputs are attenuated
by 1/7 and DC coupled to the fifth order Butterworth low pass
filters, which are used to provide shaping of the phase shift
keyed (PSK) signal. The required transmit spectral mask, at the
antenna, is -30dBc at the first side-lobe relative to the main-
lobe. An unfiltered PSK waveform would have the first side-lobe
suppressed only -13dBc. The fifth-order filters are tuned to an
approximate 7.7MHz cutoff, using a 909
fixed tuning resistor
external to the HFA3724.
Application Note 9624
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| PRISM1RC | () |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PRISM24GHZCHIPSET | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Wireless Transceiver Chip Set |
| PRISM-CHIP-SET | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| PRIXP420BB | 功能描述:IC NETWRK PROCESSR 266MHZ 492BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| PRIXP420BC | 功能描述:IC NETWRK PROCESSR 400MHZ 492BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| PRIXP420BD | 功能描述:IC NETWRK PROCESSR 533MHZ 492BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
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