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| 型號： | PR31700 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit RISC Microprocessor(32位 RISC微處理器) |
| 中文描述： | 32-BIT, 75 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | PLASTIC, LQFP-208 |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 378K |
| 代理商： | PR31700 |
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Philips Semiconductors
Preliminary specification
PR31700
32-bit RISC microprocessor
1998 May 13
20
FUNCTION SPECIFICATIONS
OUTLINE
The PR31700 consists of system support logic, integrated with the
PR3901 Processor Core designed by Philips. For details of the
system support logic and the PR3901 Processor Core, refer to the
PR31700 User’s Manual.
PR3901 PROCESSOR CORE
The PR3901 is a Philips-developed microprocessor core based on
the R3000A RISC architecture developed by MIPS Technologies,
Inc.
INSTRUCTIONS
All PR3901 Processor Core instructions are 32-bit instructions.
Apart from some coprocessor instructions, the instructions are
upwardly compatible with the R3000A. The PR3901 Processor Core
instructions can be classified into six types.
Load and store instructions
–
Transfer data between memory and general-purpose registers.
Computational instructions
–
These include arithmetic, logical, shift, multiply, divide, and
multiply-add instructions. The multiply-add instructions are
extensions to the R3000A. The multiply instructions can also
be used as three-operand instructions.
Special instructions
–
Used for system call or break point.
Jump and branch instructions
–
Change the control flow of a program. The Branch-Likely
instruction is provided as an extension to the R3000A.
Coprocessor instructions
–
Perform operations for coprocessors. The R3000A LWCz and
SWCz instructions are reserved instructions in the PR3901
Processor Core. Attempting execution generates a reserved
instruction exception. Note that the COPz, CTCz and MTCz
instructions are no-operation instructions, the CFCz and MFCz
instructions load undefined data to general purpose registers
(rt) in the PR31700.
System control coprocessor instructions
–
Perform operations on the CP0 registers to manipulate the
memory management and exception handling functions of the
processor.
REGISTERS
The PR3901 Processor Core has following registers.
32 general purpose registers (32-bit)
HI/LO registers
–
Hold the result of multiply and divide operation
PC (Program Counter)
Cause register
–
Indicates the nature of the most recent exception
EPC (Exception Program Counter) register
–
Holds the program counter at the time the exception occurred,
indicating the address where processing is to resume after the
exception processing is completed.
Status register
–
Holds the operating mode status (user mode or kernel mode),
interrupt masking status, diagnosis status and other such
information.
BadVAddr (Bad Virtual Address) register
–
Holds the most recent virtual address for which a virtual
address translation error occurred.
PRId register
–
Shows the revision number of the PR3901 Processor Core.
–
Cache register
–
Controls the instruction cache (reserved) and the data cache
auto-lock bits.
Debug register
–
Control software debug exception.
DEPC
–
Program counter for software debug exception.
MEMORY MANAGEMENT
The PR3901 Processor Core has a 4G-byte memory address
space. The 4G-byte memory space consists of a 2G-byte user area
and a 2G-byte kernel area. The kernel area contains a cache area
and an uncache area.The PR3901 Processor Core provides a
full-featured memory management unit (MMU) utilizing an on-chip
Translation Lookaside Buffer (TLB). The on-chip TLB majur
characteristics are :
32 x 64-bit wide entries
fully associative
2 entry micro TLB for instruction address translation
instruction address translation accesses full TL after micro-TLB
miss
data address translation accesses full TLB
PIPELINE
The PR3901 Processor Core pipeline consists of five stages. The
pipeline configuration enables the PR3901 Processor Core to
execute nearly all instructions in one clock.
CACHE
The PR31700 incorporates a 4K-byte instruction cache and a
1K-byte data cache. The instruction cache is direct-mapped with a
block size of 16 bytes. The data cache uses two-way set-associative
mapping with a block size of four bytes. The data cache has a lock
function that locks data in one direction. The write-through method
is used to write data back to memory.
DSP FUNCTION
The PR3901 Processor Core has a high-speed
multiplier/accumulator and supports 32-bit multiplier operations, with
64-bit accumulator in one cycle.
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