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參數(shù)資料
| 型號： | PQ48033HTA38NYS |
| 廠商： | SYNQOR INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 725K |
| 代理商： | PQ48033HTA38NYS |
Product # PQ48033HTA38
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-2UT433F Rev. A
12/03/04
Page 13
Input:
Output:
Current:
P
Package:
ackage:
35-75 V
3.3 V
38 A
Half-brick
T
Technical S
echnical Specification
pecification
side ground, Vin(-).
Start Sync (pin B): The Start Synchronization pin will allow a
more consistent start-up sequence. To operate this feature, con-
nect together the Start-Sync pins of multiple current-sharing units.
This will permit immediate start-up with loads greater than the cur-
rent limit of a single unit. Without this connection, any set of con-
verters attempting to asynchronously start (or re-start) with a load
greater than the current limit of a single unit will "hiccup". This
“hiccup” mode will continue until one converter attempts a start
at the same time as the minimum number of additional units nec-
essary to sustain the load condition. For example, three 50 amp
units starting into a 90 amp load would require two units to simul-
taneously attempt a start. The Start Sync connection synchro-
nizes these starting attempts and provides a more consistent and
reliable start-up sequence. For details about the "hiccup mode"
or repeated startup attempts, please see the "Startup Inhibit
Period" note in this Technical Specification.
Clock Sync (pin A): The External Clock Synchronization pin
provides the ability for the user to control the EMI signature and
synchronize sensitive circuitry to quiet periods in the converter
operation. With this option, the converter can be synchronized to
an external clock signal whose frequency is greater than that of
the free-running internal clock. However, substantially raising the
converter’s frequency will reduce its efficiency. Therefore, the rec-
ommended frequency range for the external clock synchroniza-
tion signal applied to this pin would be the lowest value possible
without dropping below the minimum frequencies listed below:
275 KHz for the 1.5V and 3.3V units
225 KHz for the 1.8V and 2.0V units
255 KHz for the 2.5V, 5V, 12V and 15V units
The following requirements should also be met:
The external clock signal should be referenced to the
negative input voltage, Vin(-).
The high level of the signal should be between 3.5V and
5.0V.
The low level should be between -0.5V and +1.2V.
Do not apply a clock signal lower than the specified fre-
quency.
OR Drive (pin C): This pin provides a signal which can be
used to drive an OR-ing FET and/or an auxiliary external control
circuitry. This pin may also be used as a basic "Power-Good"
signal. This pin is referenced to the secondary-side ground,
Vsense(-). The voltage at this pin tracks the output voltage but has
a value several times higher. For example, during normal oper-
ation the OR Drive voltage is at least high enough to fully gate
on a standard MOSFET, whose source voltage is equal to the out-
put voltage of the converter. With nominal output voltage, the
OR Drive signals are listed in the table below for each output volt-
age. An internal 2.7 K
source resistance will limit the current
drawn from this pin. However, the user is responsible for the
overvoltage protection of the MOSFET or other external circuitry
driven by this voltage. It is recommended that the user include a
zener diode between the gate and source of the external MOS-
FET(s) driven by the OR Drive pin. For more information, refer to
the Full Feature Application Note found on the SynQor web site
(www.synqor.com).
OR-Drive Voltages
Vout
No Load
Full Load
1.2
TBD
1.5
912
1.8
11
14
2.0
11
16
2.5
13
21
3.3
13
16
5.0
19
20
12
24
26
15
26
28
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