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參數(shù)資料
| 型號： | PPG312F-20M |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 標(biāo)準(zhǔn)邏輯 |
| 英文描述： | SPECIALTY LOGIC CIRCUIT, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 5/5頁 |
| 文件大?。?/td> | 46K |
| 代理商： | PPG312F-20M |
PPG312F
Doc #97008
DATA DELAY DEVICES, INC.
5
1/15/97
3 Mt. Prospect Ave. Clifton, NJ 07013
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25
oC
± 3oC
Load:
1 FAST-TTL Gate
Supply Voltage (Vcc): 5.0V
± 0.1V
Cload:
5pf
± 10%
Input Pulse:
High = 3.0V
± 0.1V
Threshold:
1.5V (Rising & Falling)
Low = 0.0V
± 0.1V
Source Impedance:
50
Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 10ns
Period:
PERIN = 2 x Max. Pulse Width
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
Timing Diagram For Testing
TTO
PWA
PERIN
PWIN
TRISE
TFALL
0.6V
1.5V
2.4V
1.5V
VIH
VIL
VOH
VOL
INPUT
SIGNAL
OUTPUT
SIGNAL
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