參數(shù)資料
型號： PPC5604BCLL48
廠商： Freescale Semiconductor
文件頁數(shù)： 58/109頁
文件大?。?/td> 0K
描述： MCU 32BIT 512K 48MHZ
標(biāo)準(zhǔn)包裝： 90
系列： MPC56xx Qorivva
核心處理器： e200z0h
芯體尺寸： 32-位
速度： 48MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 79
程序存儲(chǔ)器容量： 512KB（512K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 16
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 28x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Package pinouts and signal descriptions
Freescale Semiconductor
52
The
VDD(STDBY)| and dVDD(STDBY)/dt system requirement can be used to define the component used for the VDD supply
generation. The following two examples describe how to calculate capacitance size:
SR — Maximum slope on VDD during
standby exit
——
15
mV/s
VMREG
CC T Main regulator output voltage
Before exiting from
reset
—
1.32
—
V
P
After trimming
1.16
1.28
—
IMREG
SR — Main regulator current provided to
VDD_LV domain
——
—
150
mA
IMREGINT
CC D Main regulator module current
consumption
IMREG = 200 mA
—
2
mA
IMREG = 0 mA
—
1
VLPREG
CC P Low power regulator output
voltage
After trimming
1.16
1.28
—
V
ILPREG
SR — Low power regulator current
provided to VDD_LV domain
—
——
15
mA
ILPREGINT
CC D Low power regulator module
current consumption
ILPREG = 15 mA;
TA = 55 °C
——
600
A
—
ILPREG = 0 mA;
TA = 55 °C
—
5—
VULPREG
CC P Ultra low power regulator output
voltage
After trimming
1.16
1.28
—
V
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
——
—
5
mA
IULPREGINT
CC D Ultra low power regulator module
current consumption
IULPREG = 5 mA;
TA = 55 °C
——
100
A
IULPREG = 0 mA;
TA = 55 °C
—
2—
IDD_BV
CC D In-rush average current on VDD_BV
during power-up5
——
—
3006
mA
1 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2 This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage.
A typical value is in the range of 470 nF.
3 This value is acceptable to guarantee operation from 4.5 V to 5.5 V
4 External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
5 In-rush average current is seen only for short time (maximum 20 s) during power-up and on standby exit. It is
dependant on the sum of the CREGn capacitances.
6 The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must
be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
Table 25. Voltage regulator electrical characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
t
d
d VDD STDBY
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PPC5604BCLL64 功能描述:MCU 32BIT 512K 64MHZ RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MPC56xx Qorivva 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C，智能卡，UART/USART，USB 外圍設(shè)備:LED，POR，WDT 輸入/輸出數(shù):9 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件
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