參數(shù)資料
型號(hào): PPC440GRX-STA400TZ
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA680
封裝: 35 MM, THERMALLY ENHANCED, PLASTIC, BGA-680
文件頁(yè)數(shù): 2/88頁(yè)
文件大小: 1367K
代理商: PPC440GRX-STA400TZ
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
10
AMCC Proprietary
Revision 1.08 – October 15, 2007
PowerPC 440 Processor
The PowerPC 440 processor is designed for high-end applications: RAID controllers, SAN, iSCSI, routers,
switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the
128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
Up to 667MHz operation
PowerPC Book E architecture
32KB I-cache, 32KB D-cache
– UTLB Word Wide parity on data and tag address parity with exception force
Three logical regions in D-cache: locked, transient, normal
D-cache full line flush capability
41-bit virtual address, 36-bit (64GB) physical address
Superscalar, out-of-order execution
7-stage pipeline
3 execution pipelines
Dynamic branch prediction
Memory management unit
– 64-entry, full associative, unified TLB with optional parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
Debug facilities
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
24 DSP instructions
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
SRAM Controller
The internal SRAM controller (ISC) supports the following features:
One bank (Bank 0) of 16KB configurable as 4KB, 8KB or 16KB (128 bits wide)
128-bit slave attachment addressable by any PLB master
Transfers by PLB slave cycles:
– Single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters)
– 4-word line read and write
– 8-word line read and write
– Double word read and write bursts for 64-bit masters
– Quadword read and write bursts for 128-bit masters
– Slave-terminated double word and quadword fixed length bursts
– Master-terminated variable length bursts
Guarded memory access on 4 KB boundaries
Data parity checking
Data transfers occur at PLB bus speeds.
Power management
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