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參數(shù)資料
| 型號(hào)： | PPC405GPR-3KB400Z |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 405GPr Embedded Processor |
| 中文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, EBGA-456 |
| 文件頁(yè)數(shù)： | 47/57頁(yè) |
| 文件大?。?/td> | 614K |
| 代理商： | PPC405GPR-3KB400Z |
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405GPr – Power PC 405GPr Embedded Processor
AMCC
47
Revision 2.04 – September 7, 2007
Data Sheet
Notes:
1. In all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc”
means “don’t care.”
2. See “Test Conditions” on page 42 for output capacitive loading.
I/O Specifications—Group 1
(Sheet 1 of 3)
Notes:
1.
PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OV
DD
and I/O L is specified at 0.1OV
DD
. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(min)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(min)
PCI Interface
PCIAD31:0
PCIC3:0[BE3:0]
PCIClk
PCIDevSel
PCIFrame
PCIGnt0[Req]
PCIGnt1:5
PCIIDSel
PCIINT[PerWE]
PCIIRDY
PCIParity
PCIPErr
PCIReq0[Gnt]
PCIReq1:5
PCIReset
PCISErr
PCIStop
PCITRDY
Ethernet Interface
EMCMDClk
3
3
dc
3
3
0
0
dc
0
0
6
6
1
1
na
1
1
0.5
0.5
na
0.5
0.5
1.5
1.5
na
1.5
1.5
PCI Clock
PCI Clock
1
1
na
6
6
async
1
1
PCI Clock
PCI Clock
na
na
na
na
0.5
1.5
PCI Clock
1
3
na
3
3
3
0
na
0
0
0
6
dc
6
6
6
1
dc
1
1
1
na
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
1
async
1
1
1
5
0
na
na
na
na
PCI Clock
1
na
na
3
3
na
na
0
0
na
na
6
6
na
na
1
1
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
PCI Clock
PCI Clock
PCI Clock
PCI Clock
1
1
na
na
settable
1 OPB clock
period + 10ns
20
20
20
2
10.3
7.1
2, async
EMCMDIO[PHYMDIO]
100
0
1 OPB clock
period
2
2
2
10.3
7.1
EMCMDClk
2
EMCTxD3:0
EMCTxEn
EMCTxErr
PHYCol
PHYCrS
PHYRxClk
PHYRxD3:0
PHYRxDV
PHYRxErr
PHYTxClk
na
na
na
na
na
na
10.3
10.3
10.3
10.3
10.3
na
10.3
10.3
10.3
na
7.1
7.1
7.1
7.1
7.1
na
7.1
7.1
7.1
na
PHYTX
PHYTX
PHYTX
2
2
2
2, async
2, async
2, async
2
2
2
2, async
4
4
4
1
1
1
na
na
na
na
na
na
PHYRX
PHYRX
PHYRX
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