參數(shù)資料
型號: PPC405EZ-CSAfffTx
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EZ Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EZ
文件頁數(shù): 5/54頁
文件大?。?/td> 362K
代理商: PPC405EZ-CSAFFFTX
PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
AMCC Proprietary
5
Preliminary Data Sheet
Block Diagram
Figure 1. PPC405EZ Embedded Controller Functional Block Diagram
The PPC405EZ is designed using the IBM Microelectronics Blue Logic
TM
methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect
TM
Bus Architecture.
D-OCM
I-OCM
32KB
SRAM
DCR
Bus
GPIO
IIC/
BSC
Timer/
PWM
MAL
Ethernet
10/100
DMA
Controller
(4-Channel)
Bridges
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
MII
OPB/PLB
Interrupt
Controller
Arbiter
Universal
DCRs
Arbiter
UART
x2
CAN
x2
SPI
(SCP)
USB 1.1
Host/Dev
NAND
Flash
Controller
DAC
ADC
OCM
Ctrl
16KB I-Cache
16KB D-Cache
On-chip Peripheral Bus (OPB)
Processor Local Bus (PLB) 64 bit, PLB3
PowerPC
405 Core
IEEE
1588
PTP
External
Bus
Controller
PHY
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