參數(shù)資料
型號: PPC405EX-NpAfffTx
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EX Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EX
文件頁數(shù): 6/67頁
文件大小: 457K
代理商: PPC405EX-NPAFFFTX
PPC405EX – PowerPC 405EX Embedded Processor
6
AMCC Proprietary
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Address Maps
The PPC405EX incorporates two address maps. The first address map defines the possible use of addressable
memory regions that the processor can access. The second address map defines Device Configuration Register
(DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EX processor through
the use of
mtdcr
and
mfdcr
instructions.
Table 1. System Memory Address Map (4GB System Memory)
Function
Subfunction
Start Address (Hex)
0 0000 0000
0 8000 0000
0 9000 0000
0 EF60 0000
0 EF60 0200
0 EF60 0208
0 EF60 0300
0 EF60 0308
0 EF60 0400
0 EF60 0420
0 EF60 0500
0 EF60 0520
0 EF60 0600
0 EF60 0606
0 EF60 0700
0 EF60 0740
0 EF60 0800
0 EF60 0880
0 EF60 0900
0 EF60 0A00
0 EF60 0B00
0 EF60 0C04
0 EF61 0000
0 EF62 0000
0 EF62 0100
0 EF6C 0000
0 EF70 0000
0 EF78 0000
0 F000 0000
0 FFE0 0000
End Address (Hex)
0 7FFF FFFF
0 8FFF FFFF
0 EF5F 00FF
0 EF60 01FF
0 EF60 0207
0 EF60 02FF
0 EF60 0307
0 EF60 03FF
0 EF60 041F
0 EF60 04FF
0 EF60 051F
0 EF60 05FF
0 EF60 0605
0 EF60 06FF
0 EF60 073F
0 EF60 07FF
0 EF60 087F
0 EF60 08FF
0 EF60 09FF
0 EF60 0AFF
0 EF60 0C03
0 EF60 FFFF
0 EF61 FFFF
0 EF62 00FF
0 EF6B FFFF
0 EF6F FFFF
0 EF77 FFFF
0 EFFF FFFF
0 FFDF FFFF
0 FFFF FFFF
Size
2GB
256MB
1.5GB
512B
8B
248B
8B
248B
32B
224B
32B
224B
6B
250B
64B
192B
128B
128B
256B
256B
260B
62KB
64KB
256B
640KB
256KB
512KB
8.9MB
254MB
2MB
Local Memory
EBC
PCI Express
DDR 1/2 SDRAM
OPB Peripherals
GPT
UART 0
Reserved
UART 1
Reserved
IIC 0
Reserved
IIC 1
Reserved
SCP
Reserved
OPB Arbiter
Reserved
GPIO
Reserved
Ethernet 0
Ethernet 1
RGMII Bridge
Reserved
PKA +TRNG
PCI Express Interrupt Handler
Reserved
USB OTG
Security
Reserved
EBC Memory
EBC Memory—Boot ROM
PLB/AHB Peripherals
EBC
Notes:
1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. After the boot process, software may reassign the boot memory regions for other uses.
3. PCI Express can use PLB address range 1 0000 0000 to FFFF FFFF FFFF FFFF even though the CPU can not access it.
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