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參數(shù)資料
| 型號： | PNX3000HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Analog front end for digital video processors |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-425-1, MS-026, LQFP-128 |
| 文件頁數(shù)： | 35/51頁 |
| 文件大?。?/td> | 285K |
| 代理商： | PNX3000HL |
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2004 Oct 04
35
Philips Semiconductors
Preliminary specification
Analog front end for digital video
processors
PNX3000
Timing circuit
HV
INPUT SIGNALS
:
PINS
HV_PRIM
AND
HV_SEC;
NOTES
29
AND
30
Timing specification for HV pulses coming from digital video processor; see Fig.8
t
(HV-sync)
time between start HV
pulse and start of
horizontal sync pulse on
CVBS/Y signal
width of HV pulses
1f
H
TV mode
2f
H
mode; HDTV = 0
2f
H
mode; HDTV = 1
0.6
0.3
0.3
μ
s
μ
s
μ
s
t
W(HV)
1f
H
TV mode
normal lines
clamp disable lines
vsync lines
2f
H
mode HDTV = 0
normal lines
clamp disable lines
vsync lines
2f
H
mode; HDTV = 1
normal lines
clamp disable lines
vsync lines
72
128
288
ck
ck
ck
36
64
144
ck
ck
ck
20
44
144
ck
ck
ck
Detection of clamp disable lines
t
det(clamp)(dis)
clamp disable detection
1f
H
TV mode
2f
H
mode; HDTV = 0
2f
H
mode; HDTV = 1
80
40
24
ck
ck
ck
Detection of vsync lines
t
det(vsync)
vsync detection
1f
H
TV mode
2f
H
mode; HDTV = 0
2f
H
mode; HDTV = 1
255
136
136
ck
ck
ck
Internal clamp pulses
t
d(HV-clamp)
delay between start of
HV pulse and start of
clamp pulse
1f
H
TV mode
2f
H
mode; HDTV = 0
2f
H
mode; HDTV = 1
1f
H
TV mode
2f
H
mode; HDTV = 0
2f
H
mode; HDTV = 1
80
40
24
44
22
17
ck
ck
ck
ck
ck
ck
t
W(clamp)
width of clamp pulse
C
RYSTAL REFERENCE FREQUENCY INPUT
:
PIN
XREF
R
i
C
i
V
i(p-p)
input resistance
input capacitance
input signal amplitude
(peak-to-peak value)
25
1
35
3
45
3.5
k
pF
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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