參數(shù)資料
型號(hào)： PNX2000HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Audio video input processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, MS-026, LQFP-144
文件頁數(shù)： 21/31頁
文件大?。?/td> 244K
代理商： PNX2000HL
9397 750 13928
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 – 23 August 2004
21 of 31
Philips Semiconductors
PNX2000
Audio video input processor
[1]
[2]
[3]
Allowed SCK/WS ratios are 32, 48, 64, 128 and 256 SCK periods per WS period.
All timings relative to the rising edge of SCK.
See
Section 10.4
for waveforms.
t
h(DATA)
data hold at Rx
40 pF load
-
-
4.9
ns
I
2
S
f
s
audio sample frequency
-
32
48
48
kHz
f
SCK
SCK frequency
I
2
S-bus master mode
-
64f
s
-
-
f
SCK
SCK frequency
I
2
S-bus slave mode
32f
s
64f
s
256f
s
-
DF
SCK
SCK duty factor
I
2
S-bus master mode
40
50
60
%
DF
SCK
SCK duty factor
I
2
S-bus slave mode
35
-
65
%
t
RSCK
SCK rise / fall time
I
2
S-bus master mode; C
load
= 30 pF
-
-
5
ns
t
RSCK
SCK rise / fall time
I
2
S-bus slave mode; f
SCK
= 3.072 MHz -
-
50
ns
t
d
delay time: SCK to WS and SD
outputs
[2]
hold time: SCK to WS and SD inputs -
T
SCK
= 1/f
SCK
0.3
0.5
0.7
T
SCK
t
h
0
-
-
ns
t
s
setup time: WS and SD inputs to
SCK
T
SCK
= 1/f
SCK
0.2
-
-
T
SCK
I
2
D
f
clock(WORD)
word clock frequency
-
-
13.5
-
MHz
WL
word length
-
-
44
-
bit
DR
data rate
-
-
594
-
Mbit/s
f
clock(BIT)
bit clock freq.
-
-
297
-
MHz
JTAG Clock Reset
t
low
Time RESET_N should be below
V
trip_high
before internal reset = 1.
Time RESET_N should be above
V
trip_high
before internal reset = 0
(after t
pulse
).
Time before PNX2000 internal reset
= 0
[3]
.
RESET_SEL = 0
-
-
11
μ
s
t
high
RESET_SEL = 0
-
-
2
μ
s
t
pulse
RESET_SEL = 0
200
-
-
ns
Table 23:
Symbol
Dynamic characteristics
…continued
Parameter
Conditions
Min
Typ
Max
Unit
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