參數(shù)資料
型號: PLUS405-45N
廠商: NXP SEMICONDUCTORS
元件分類: PLD
英文描述: Programmable logic sequencers 16 】 64 】 8
中文描述: OT PLD, 15 ns, PDIP28
封裝: 0.600 INCH, PLASTIC, DIP-28
文件頁數(shù): 9/20頁
文件大?。?/td> 327K
代理商: PLUS405-45N
Philips Semiconductors
Product specification
PLUS405-37/-45
Programmable logic sequencers
(16
×
64
×
8)
1996 Nov 12
9
AC ELECTRICAL CHARACTERISTICS
R
1
= 470
, R
2
= 1k
, C
L
= 30pF, 0
°
C
T
amb
+75
°
C, 4.75V
V
CC
5.25V
LIMITS
SYMBOL
PARAMETER
FROM
TO
PLUS405-37
PLUS405-45
UNIT
MIN
TYP
1
MAX
MIN
TYP
1
MAX
Pulse width
t
CKH1
Clock High; CLK1 (Pin 1)
CK+
CK–
10
8
8.5
7
ns
t
CKL1
Clock Low; CLK1 (Pin 1)
CK–
CK+
10
8
8.5
7
ns
t
CKP1
CLK1 Period
CK+
CK+
20
16
17
14
ns
t
CKH2
Clock High; CLK2 (Pin 4)
CK+
CK–
10
8
10
8
ns
t
CKL2
Clock Low; CLK2 (Pin 4)
CK–
CK+
10
8
10
8
ns
t
CKP2
CLK2 Period
CK+
CK+
20
16
20
16
ns
t
INITH
Initialization pulse
INIT–
INIT+
15
10
15
8
ns
Setup time
t
IS1
Input
Input
±
CK+
15
12
12
10
ns
t
IS2
Input
(through Complement Array)
Input
±
CK+
25
20
22
18
ns
t
VS
Power-on preset
V
CC
+
CK–
0
–10
0
–10
ns
t
VCK
Clock resume
(after Initialization)
INIT–
CK–
0
–5
0
–5
ns
t
NVCK
Clock lockout
(before Initialization)
CK–
INIT–
15
5
15
5
ns
Hold time
t
IH
Input
CK+
Input
±
0
–5
0
–5
ns
Propagation delay
t
CKO1
Clock1 (Pin 1)
CK1+
Output
±
10
12
8
10
ns
t
CKO2
t
OE2
t
OD2
Clock2 (Pin 4)
CK2+
Output
±
12
15
10
12
ns
Output Enable
OE–
Output –
12
15
12
15
ns
Output Disable
OE+
Output +
12
15
12
15
ns
t
INIT
Initialization
INIT+
Output +
15
20
15
20
ns
t
PPR
Power-on Preset
V
CC
+
Output +
0
10
0
10
ns
Notes on following page
相關(guān)PDF資料
PDF描述
PLUS405-55 Programmable logic sequencer 16 】 64 】 8
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