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參數(shù)資料
| 型號(hào)： | PLS100 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable logic arrays 16 】 48 】 8 |
| 中文描述： | 可編程邏輯陣列16】48】8 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | PLS100 |
Philips Semiconductors Programmable Logic Devices
Product specification
PLS100/PLS101
Programmable logic arrays
(16
×
48
×
8)
October 22, 1993
52
DC ELECTRICAL CHARACTERISTICS
0
°
C
≤
T
amb
≤
+75
°
C, 4.75V
≤
V
CC
≤
5.25V
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
Input voltage
2
V
IH
High
V
CC
= MAX
2.0
V
V
IL
Low
V
CC
= MIN
0.8
V
V
IC
Output voltage
2
Clamp
3
V
CC
= MIN, I
IN
= –12mA
–0.8
–1.2
V
V
CC
= MIN
V
OH
High (PLS100)
4
I
OH
= –2mA
2.4
V
V
OL
Low
5
I
OL
= 9.6mA
0.35
0.45
V
Input current
I
IH
High
V
IN
= 5.5V
< 1
25
μ
A
I
IL
Low
V
IN
= 0.45V
–10
–100
μ
A
Output current
I
O(OFF)
Hi-Z state (PLS100)
CE = High, V
CC
= MAX
V
OUT
= 5.5V
1
40
μ
A
V
OUT
= 0.45V
–1
–40
μ
A
I
OS
Short circuit (PLS100)
3, 6
CE = Low, V
OUT
= 0V
–15
–70
mA
I
CC
V
CC
supply current
7
V
CC
= MAX
120
170
mA
Capacitance
CE = High, V
CC
= 5.0V
C
IN
Input
V
IN
= 2.0V
8
pF
C
OUT
Output
V
OUT
= 2.0V
17
pF
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25
°
C.
2. All voltage values are with respect to network ground terminal.
3. Test one pin at a time.
4. Measured with V
IL
applied to CE and a logic high stored.
5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor
to V
.
6. Duration of short circuit should not exceed 1 second.
7. I
CC
is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open.
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