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參數(shù)資料
| 型號： | PLL0930A |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 960 MHz, QMA14 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 239K |
| 代理商： | PLL0930A |
PLL0930A
Basestations
Mobile Radios
Satellite Communications
5
40
900
-65
0.75
-15
5
1
-40 to +85
Frequency Range
RMS Phase Error (100 Hz - 100 KHz)
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
Package Style
PLL
MHz
°
dBc
mSec
°C
Vdc
mA
Supply Voltage (Vcc, nom.)
Supply Current (Icc, typ.)
All specifications are typical unless otherwise noted and subject to change without notice.
PHASE NOISE (1 Hz BW, typical)
Z-Communications, Inc.
All rights reserved
Page 1
PHASE LOCKED LOOP
FEATURES
APPLICATIONS
PERFORMANCE SPECIFICATIONS
VALUE
UNITS
POWER SUPPLY REQUIREMENTS
APPLICATION NOTES
900
MHz
Step Size:
100 KHz
- Style Package
PLL
A1
Rev
AN-107 : How to Solder Z-COMM VCOs / PLLs
AN-115 : Mounting and Grounding of Z-COMM PLLs
AN-116 : How to Program Z-COMM PLLs
NOTES:
Reference Oscillator Signal: 5 MHz<
fosc<40 MHz
9939 Via Pasar San Diego, CA 92126
TEL (858) 621-2700
FAX (858) 621-2722
Power Output
3±2
dBm
Load Impedance
50
Step Size
100
KHz
HIGH
960
-
Frequency Range:
-
960
Charge Pump Output Current
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