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參數(shù)資料
| 型號： | PL-2521 |
| 英文描述： | PL-2521 Hi-Speed USB Cellular Mate and Flash Disk Controller Product Datasheet v1.0|Doc - Data Sheet?-- ?PL-2521 Hi-Speed USB CellularMate and Flash Disk Controller |
| 中文描述： | 特等- 2521高速USB細(xì)胞伴侶和U盤控制器產(chǎn)品數(shù)據(jù)表1.0 |文件-數(shù)據(jù)表？ - ？特等- 2521高速USB CellularMate和U盤控制器 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 190K |
| 代理商： | PL-2521 |
Release Date
August 2003
ds_pl2507_v13
PL-2507 Product Datasheet
- 7 -
Document Version 1.3
4.1.1 USB2.0 PHY Related Pins
Table 4-1-1 USB2.0 PHY Related Pins
Symbol
Type
Pin No
Description
XSCI
I
42
Clock in or CMOS oscillator input.
XSCO
B
43
CMOS oscillator output.
RREF
A
46
PLL Reference level
DP
B
48
High speed DPLUS signal
DM
B
47
High speed DMINUS signal
RPU
A
50
1.5 K-ohm Pull-up resistor
DPRS
B
52
Full speed DPLUS signal
DMRS
B
51
Full speed DMINUS signal
VCCK
P
40
Digital Power 2.5v
GNDK
P
41
Digital Ground
AVCC1,
AVCC2,
AVCC3
P
44,
53,
55
Analog Power 3.3v for on-chip PHY
AGND1,
AGND2,
AGND3
P
45,
49,
54
Analog Ground for on-chip USB PHY.
4.1.2 IDE Interface Related Pins
Table 4-1-2 IDE Interface Related Pins
Symbol
Type
Pin No
Description
DD[15:0]
B
17,19,
21,23,
26,28,
30,33,
34,31,
29,27,
24,22,
20,18
16 pins Data bus of IDE interface
DA[2:0]
T
4,5,6
DA, Data Address pins of IDE interface. Will be in high
impedance state until USB connection.
CSJ[1:0]
T
2,3
CS_, Chip Select pins of IDE interface. Will be in
high-impedance state until USB connection.
USB_PWR
I
62
Power signal from USB connection.
ATA_RSTJ
T
15
Hardware reset pin of IDE interface. Will be in high
impedance state until USB connection.
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