參數(shù)資料
型號(hào): PIC24HJ12GP201-I/SO
廠商: Microchip Technology
文件頁(yè)數(shù): 5/262頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 12KB 18SOIC
產(chǎn)品培訓(xùn)模塊: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 42
系列: PIC® 24H
核心處理器: PIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 12KB(4K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 648 (CN2011-ZH PDF)
配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
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PIC24HJ12GP201/202
DS70282E-page 102
2007-2011 Microchip Technology Inc.
10.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any 5V-tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
See “Pin Diagramsfor the available pins and their
functionality.
10.2
Configuring Analog Port Pins
The AD1PCFG and TRIS registers control the opera-
tion of the Analog-to-Digital (A/D) port pins. The port
pins that are desired as analog inputs must have their
corresponding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL)
will be converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP. An example is shown in Example 10-1.
10.3
Input Change Notification
The input change notification function of the I/O ports
allows the PIC24HJ12GP201/202 devices to generate
interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature
can detect input change-of-states even in Sleep mode,
when the clocks are disabled. Depending on the device
pin count, up to 21 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
Four control registers are associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
EXAMPLE 10-1:
PORT WRITE/READ EXAMPLE
Note:
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
MOV
0xFF00, W0
; Configure PORTB<15:8> as inputs
MOV
W0, TRISBB
; and PORTB<7:0> as outputs
NOP
; Delay 1 cycle
btss
PORTB, #13
; Next Instruction
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PIC24HJ12GP202E/ML 制造商:MICROCHIP 制造商全稱(chēng):Microchip Technology 功能描述:High-Performance, 16-Bit Microcontrollers
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