參數(shù)資料
型號： PIC24FJ64GA110T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 31/330頁
文件大?。?/td> 0K
描述： MCU PIC 64KB FLASH 100TQFP
標準包裝： 1,200
系列： PIC® 24F
核心處理器： PIC
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，IrDA，LIN，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 85
程序存儲器容量： 64KB（22K x 24）
程序存儲器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
包裝： 帶卷 (TR)
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PIC24FJ256GA110 FAMILY
DS39905E-page 126
2010 Microchip Technology Inc.
9.2.2
IDLE MODE
Idle mode has these features:
The CPU will stop executing instructions.
The WDT is automatically cleared.
The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
).
If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
Any interrupt that is individually enabled
Any device Reset
A WDT time-out
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAV instruction or
the first instruction in the ISR.
9.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV
instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
9.3
Doze Mode
Generally, changing clock speed and invoking one of
the power-saving modes are the preferred strategies
for reducing power consumption. There may be
circumstances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors,
while using a power-saving mode may stop
communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock contin-
ues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed while the CPU clock speed is reduced.
Synchronization between the two clock domains is
maintained, allowing the peripherals to access the
SFRs while the CPU executes code at a slower rate.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>).
There
are
eight
possible
configurations, from 1:1 to 1:128, with 1:1 being the
default.
It is also possible to use Doze mode to selectively
reduce power consumption in event driven applica-
tions. This allows clock-sensitive functions, such as
synchronous communications, to continue without
interruption while the CPU Idles, waiting for something
to invoke an interrupt routine. Enabling the automatic
return to full-speed CPU operation on interrupts is
enabled by setting the ROI bit (CLKDIV<15>). By
default, interrupt events have no effect on Doze mode
operation.
9.4
Selective Peripheral Module
Control
Idle and Doze modes allow users to substantially
reduce power consumption by slowing or stopping the
CPU clock. Even so, peripheral modules still remain
clocked and thus consume power. There may be cases
where the application needs what these modes do not
provide: the allocation of power resources to CPU
processing with minimal power consumption from the
peripherals.
PIC24F devices address this requirement by allowing
peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
done with two control bits:
The Peripheral Enable bit, generically named
“XXXEN”, located in the module’s main control
SFR.
The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
the PMD Control registers.
Both bits have similar functions in enabling or disabling
its associated module. Setting the PMD bit for a module
disables all clock sources to that module, reducing its
power consumption to an absolute minimum. In this
state, the control and status registers associated with
the peripheral will also be disabled, so writes to those
registers will have no effect and read values will be
invalid. Many peripheral modules have a corresponding
PMD bit.
In contrast, disabling a module by clearing its XXXEN
bit disables its functionality, but leaves its registers
available to be read and written to. This reduces power
consumption, but not by as much as setting the PMD
bit does. Most peripheral modules have an enable bit;
exceptions include input capture, output compare and
RTCC.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the
control bit of the generic name format, “XXXIDL”. By
default, all modules that can operate during Idle mode
will do so. Using the disable on Idle feature allows
further reduction of power consumption during Idle
mode, enhancing power savings for extremely critical
power applications.
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