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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC24FJ64GA004-I/ML |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 25/52闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 64KB 44QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Graphics LCD System and PIC24 Interface Asynchronous Stimulus |
| 鐗硅壊鐢�(ch菐n)鍝侊細 | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 绯诲垪锛� | PIC® 24F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 16-浣� |
| 閫熷害锛� | 32MHz |
| 閫ｉ€氭€э細 | I²C锛孭MP锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孡VD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 35 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 64KB锛�22K x 24锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 13x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-VQFN 瑁搁湶鐒婄洡(p谩n) |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 647 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 876-1004-ND - PIC24 BREAKOUT BOARD DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28 AC164336-ND - MODULE SOCKET FOR PM3 28/44QFN DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 |
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2008 Microchip Technology Inc.
DS39768D-page 31
PIC24FJXXXGA0XX
ICS(1)
CW1<8>
ICD Pin Placement Select bit
11
= ICD EMUC/EMUD pins are shared with PGC1/PGD1
10
= ICD EMUC/EMUD pins are shared with PGC2/PGD2
01
= ICD EMUC/EMUD pins are shared with PGC3/PGD3
00
= Reserved; do not use
IESO
CW2<15>
Internal External Switchover bit
1
= Two-Speed Start-up enabled
0
= Two-Speed Start-up disabled
IOL1WAY(1)
CW2<4>
IOLOCK Bit One-Way Set Enable bit
0
= The OSCCON<IOLOCK> bit can be set and cleared as needed (provided
an unlocking sequence is executed)
1
= The OSCCON<IOLOCK> bit can only be set once (provided an unlocking
sequence is executed). Once IOLOCK is set, this prevents any possible
future RP register changes
JTAGEN
CW1<14>
JTAG Enable bit
1
= JTAG enabled
0
= JTAG disabled
OSCIOFNC
CW2<5>
OSC2 Pin Function bit (except in XT and HS modes)
1
= OSC2 is clock output
0
= OSC2 is general purpose digital I/O pin
SOSCSEL1:
SOSCSEL0(2)
CW2<12:11>
Secondary Oscillator Power Mode Select bits
11
= Default (high drive strength) mode
01
= Low-Power (low drive strength) mode
x0
= Reserved; do not use
POSCMD1:
POSCMD0
CW2<1:0>
Primary Oscillator Mode Select bits
11
= Primary oscillator disabled
10
= HS Crystal Oscillator mode
01
= XT Crystal Oscillator mode
00
= EC (External Clock) mode
WDTPOST3:
WDTPOST0
CW1<3:0>
Watchdog Timer Prescaler bit
1111
= 1:32,768
1110
= 1:16,384
.
0001
= 1:2
0000
= 1:1
WDTPRE
CW1<4>
Watchdog Timer Postscaler bit
1
= 1:128
0
= 1:32
WINDIS
CW1<6>
Windowed WDT bit
1
= Watchdog Timer in Non-Window mode
0
= Watchdog Timer in Window mode; FWDTEN must be 鈥�1鈥�
WUTSEL1:
WUTSEL0(2)
CW2<14:13>
Voltage Regulator Standby Mode Wake-up Time Select bits
11
= Default regulator wake time used
01
= Fast regulator wake time used
x0
= Reserved; do not use
TABLE 4-2:
PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
Note 1:
Available on 28 and 44-pin packages only.
2:
Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| PIC24FJ64GA004T-I/ML | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 64KB Flash 8192bytes-RAM 35I/O RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC24FJ64GA004T-I/PT | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 64KB Flash 8192bytes-RAM 35I/O RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC24FJ64GA006 | 鍒堕€犲晢:MICROCHIP 鍒堕€犲晢鍏ㄧū:Microchip Technology 鍔熻兘鎻忚堪:General Purpose, 16-Bit Flash Microcontrollers |
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| PIC24FJ64GA006-I/PT | 鍔熻兘鎻忚堪:16浣嶅井鎺у埗鍣� - MCU 64KB 53 I/O RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:RISC 铏曠悊鍣ㄧ郴鍒�:MSP430FR572x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:16 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:24 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:8 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:VQFN-40 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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