參數(shù)資料
型號(hào): PIC24FJ64GA002-I/SP
廠商: Microchip Technology
文件頁(yè)數(shù): 14/52頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KB 28-DIP
產(chǎn)品培訓(xùn)模塊: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 64KB(22K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 647 (CN2011-ZH PDF)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164337-ND - MODULE SOCKET FOR PM3 40DIP
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
2008 Microchip Technology Inc.
DS39768D-page 21
PIC24FJXXXGA0XX
3.7
Writing Configuration Words
The PIC24FJXXXGA0XX family configuration is stored
in Flash Configuration Words at the end of the user
space program memory and in multiple register
Configuration Words located in the test space.
These registers reflect values read at any Reset from
program memory locations. The values can be changed
only by programming the content of the corresponding
Flash Configuration Word and resetting the device. The
Reset forces an automatic reload of the Flash stored
configuration
values
by
sequencing
through
the
dedicated Flash Configuration Words and transferring
the data into the Configuration registers. To change the
values of the Flash Configuration Word once it has been
programmed, the device must be Chip Erased, as
and reprogrammed to the desired value. It is not
possible to program a ‘0’ to ‘1’, but they may be
programmed from a ‘1’ to ‘0’ to enable code protection.
Table 3-7 shows the ICSP programming details for pro-
gramming the Configuration Word locations, including
the serial pattern with the ICSP command code which
must be transmitted, Least Significant bit first, using the
PGCx and PGDx pins (see Figure 3-2).
In Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for programming of
code memory. In Step 3, the 24-bit starting destination
address for programming is loaded into the TBLPAG
register and W7 register.
The TBLPAG register must be loaded with the
following:
96 and 64 Kbyte devices – 00h
128 Kbyte devices – 01h
To verify the data by reading the Configuration Words
after performing the write in order, the code protection
bits initially should be programmed to a ‘1’ to ensure
that the verification can be performed properly. After
verification is finished, the code protection bit can be
programmed to a ‘0’ by using a word write to the
appropriate Configuration Word.
TABLE 3-6:
DEFAULT CONFIGURATION
REGISTER VALUES
Address
Name
Default Value
Last Word
CW1
7FFFh(1)
Last Word – 2
CW2
FFFFh
Note 1:
CW1<15> is reserved and must be
programmed to ‘0’.
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