參數(shù)資料
型號: PIC24FJ64GA002-I/SO
廠商: Microchip Technology
文件頁數(shù): 23/52頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KB 28SOIC
產(chǎn)品培訓模塊: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝: 27
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 64KB(22K x 24)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 647 (CN2011-ZH PDF)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164339-ND - MODULE SKT FOR PM3 28SOIC
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
2008 Microchip Technology Inc.
DS39768D-page 3
PIC24FJXXXGA0XX
2.2
Program Memory Write/Erase
Requirements
The Flash program memory on the PIC24FJXXXGA0XX
devices has a specific write/erase requirement that must
be adhered to for proper device operation. The rule is
that any given word in memory must not be written more
than twice before erasing the page in which it is located.
Thus, the easiest way to conform to this rule is to write
all the data in a programming block within one write
cycle. The programming methods specified in this
specification comply with this requirement.
2.3
Pin Diagrams
The pin diagrams for the PIC24FJXXXGA0XX family
are shown in the following figures. The pins that are
required for programming are listed in Table 2-1 and
are shown in bold letters in the figures. Refer to the
appropriate device data sheet for complete pin
descriptions.
TABLE 2-1:
PIN DESCRIPTIONS (DURING PROGRAMMING)
Note:
Writing to a location multiple times without
erasing is not recommended.
Pin Name
During Programming
Pin Name
Pin Type
Pin Description
MCLR
P
Programming Enable
ENVREG
I
Enable for On-Chip Voltage Regulator
DISVREG(1)
DISVREG
I
Disable for On-Chip Voltage Regulator
VDD and AVDD(2)
VDD
P
Power Supply
VSS and AVSS(2)
VSS
PGround
VDDCORE
P
Regulated Power Supply for Core
PGC1
PGC
I
Primary Programming Pin Pair: Serial Clock
PGD1
PGD
I/O
Primary Programming Pin Pair: Serial Data
PGC2
PGC
I
Secondary Programming Pin Pair: Serial Clock
PGD2
PGD
I/O
Secondary Programming Pin Pair: Serial Data
Legend: I = Input, O = Output, P = Power
Note 1:
Applies to 28 and 44-pin devices only.
2:
All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
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