參數(shù)資料
型號: PIC24FJ128GB110-I/PT
廠商: Microchip Technology
文件頁數(shù): 22/22頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 100TQFP
標(biāo)準(zhǔn)包裝: 119
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 83
程序存儲器容量: 128KB(43K x 24)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 648 (CN2011-ZH PDF)
配用: 876-1004-ND - PIC24 BREAKOUT BOARD
DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
MA240014-ND - MODULE PLUG-IN PIC24
2008-2011 Microchip Technology Inc.
DS80369N-page 9
PIC24FJ256GB110 FAMILY
23. Module: SPI (Enhanced Buffer Modes)
If the SPIx event interrupt is configured to occur
when
the
enhanced
FIFO
buffer
is
full
(SISEL<2:0> = 111), the interrupt may actually
occur when the 7th byte is written to the buffer,
instead of the 8th byte. The other enhanced buffer
interrupts function as previously described.
Work around
Do not use the Full Buffer Interrupt mode. The
SPITBF bit (SPIxSTAT<1>) reliably indicates when
the enhanced FIFO buffer is full and can be polled
instead of using the Full Buffer Interrupt mode.
Affected Silicon Revisions
24. Module: A/D Converter
When using PGEC1 and PGED1 to debug an
application on any 64-pin devices in this family, all
voltage references will be disabled. This includes
VREF+, VREF-, AVDD and AVSS. Any A/D
conversion will always equal 0x3FF.
Work around
Use PGEC2 and PGED2 to debug any A/D
functionality.
Affected Silicon Revisions
25. Module: SPI (Enhanced Buffer Mode)
In Enhanced Master mode, the SRMPT bit
(SPIxSTAT<7>) may erroneously become set for
several clock cycles in the middle of a FIFO transfer,
indicating that the shift register is empty when it is
not. This happens when both SPIx clock prescalers
are set to values other than their maximum
(SPIxCON<4:2> ≠ 000 and SPIxCON<1:0> ≠ 00).
Work around
Set SISEL<2:0> (SPIxSTAT<4:2>) to ‘101’. This
configures the module to generate an SPIx event
interrupt whenever the last bit is shifted out of the
shift register. When the SPIxIF flag becomes set,
the shift register is empty.
Affected Silicon Revisions
26. Module: Core (Code Protection)
When general segment code protection has been
enabled (GCP Configuration bit is programmed),
applications are unable to write to the first
512 bytes of the program memory space (0000h
through 0200h). In applications that may require
the interrupt vectors to be changed during run
time, such as bootloaders, modifications to the
Interrupt Vector Tables (IVT) will not be possible.
Work around
Create two new Interrupt Vector Tables, one each
for the IVT and AIVT, in an area of program space
beyond the affected region. Map the addresses in
the old vector tables to the new tables. These new
tables can then be modified as needed to the
actual addresses of the ISRs.
Affected Silicon Revisions
27. Module: CTMU (A/D Trigger)
The CTMU may not trigger an automatic A/D con-
version after the current source is turned off. This
happens even when the A/D trigger control bit,
CTTRIG (CTMUCON<8>), has been set.
Work around
Perform a manual A/D conversion by clearing the
SAMP bit (AD1CON1<1>) immediately after the
CTMU current source has been stopped.
Affected Silicon Revisions
A3
A5
A6
X
Note:
This issue only applies to 64-pin devices
in
this
family
(PIC24FJ256GB106,
PIC24FJ192GB106,
and
PIC24FJ64GB106).
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
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