參數(shù)資料
型號(hào): PIC24FJ128GA110T-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 11/18頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 100TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 128KB(43K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 帶卷 (TR)
配用: MA240015-ND - BOARD MCV PIM FOR 24F256GA
DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
其它名稱: PIC24FJ128GA110T-I/PTTR
PIC24FJ256GA110 FAMILY
DS80368L-page 2
2008-2011 Microchip Technology Inc.
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Issue Summary
Affected Revisions(1)
A3
A5
A6
Core
RAM Operation
RAM issues in Doze mode.
X
Core
BOR
BOR issues in enabled on-chip regulator.
X
JTAG
Device
Programming
JTAG issues in device programming.
X
UART
Framing errors in UART.
X
I/O
PORTB
RB5 issues in open-drain operation.
X
SPI
Master mode
Early one-half clock cycles.
X
CTMU
CTMU issues as a trigger source.
X
UART
UERIF Interrupt
UART error interrupt issue.
X
UART
FIFO Error Flags
Error bits settings for receive FIFO.
X
SPI
Enhanced Buffer
modes
Errors in enhanced buffer interrupts.
X
UART
IrDA
Issues in 8-bit mode using IrDA endec.
X
UART
IrDA
Framing errors in 8-bit mode using IrDA
endec.
X
UART
IrDA
Transmission errors in 9-bit mode using IrDA
endec.
X
Core
Instruction Set
Read-After-Write stall conditions inside a
REPEAT
loop.
XXX
Memory
Program Space
Visibility
False error trap conditions when accessing
data in the PSV.
X
ICSP
Inability of the ICSP/ICD port pair to read or
program.
X
RTCC
Unexpected decrementing of the Alarm
Repeat Counter.
X
I2C
Module
Master mode
Acknowledgement issues in addressing slave
device.
X
I2C
Module
Slave mode
Acknowledgement issues in Slave mode.
X
A/D Converter
Debugging issues on 64-pin devices.
X
SPI
Enhanced Buffer
mode
FIFO transfer issues in Enhanced Master
mode.
X
Core
Code Protection
Applications unable to write when General
Segment Code Protection has been enabled.
X
SPI/PPS
ALTRP/ASCK1 functionality is not supported.
X
Oscillator
LPRC
Issues with LPRC automatic restart following
BOR.
X
CTMU
A/D Trigger
Issues in the CTMU in triggering automatic
A/D conversion.
X
Output
Compare
Single missed compare events under certain
conditions.
X
Interrupts
INTx
External interrupts missed when writing to
INTCON2.
XXX
A/D Converter
Module continues to draw current when
disabled.
XXX
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
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