
CHAPTER 5 BUS CONTROL FUNCTION
User’s Manual U15905EJ2V1UD
198
Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
A1
Undefined
A1
A2
T2
T3
TI
Note
TH
TI
Note
T1
T2
T3
D1
CLKOUT
HLDRQ
HLDAK
A23 to A16
ASTB
CS3 to CS0
AD15 to AD0
RD
Undefined
A2
D2
1111
Note
This idle state (TI) does not depend on the BCC register settings.
Remarks 1. Refer to Table 2-3 for the pin statuses in the bus hold mode.
2. The broken lines indicate high impedance.