
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
223
(2) Overflow
When the TMn register has counted the count clock from FFFFH to 0000H, the OVFn bit of the TMCn0 register
is set (1), and an overflow interrupt (INTOVFn) is generated at the same time (n = 0, 1). However, if the CCn0
register is set to compare mode (CMSn0 bit = 1) and to the value FFFFH when match clearing is enabled
(CCLRn bit = 1), then the TMn register is considered to be cleared and the OVFn bit is not set (1) when the
TMn register changes from FFFFH to 0000H. Also, the overflow interrupt (INTOVFn) is not generated .
When the TMn register is changed from FFFFH to 0000H because the TMCEn bit changes from 1 to 0, the
TMn register is considered to be cleared, but the OVFn bit is not set (1) and no INTOVFn interrupt is
generated.
Also, timer operation can be stopped after an overflow by setting the OSTn bit of the TMCn1 register to 1.
When the timer is stopped due to an overflow, the count operation is not restarted until the TMCEn bit of the
TMCn0 register is set (1).
Operation is not affected even if the TMCEn bit is set (1) during a count operation.
Remark
n = 0, 1
Figure 7-3. Operation After Overflow (When OSTn = 1)
Overflow
Count
start
Overflow
FFFFH
TMn
0
INTOVFn
OSTn
← 1
TMCEn
← 1
TMCEn
← 1
Remark
n = 0, 1