CHAPTER 6 CLOCK GENERATION FUNCTION
User’s Manual U15905EJ2V1UD
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(2) Prescaler compare register (PRSCM)
This is an 8-bit compare register.
It can be read or written in 8-bit or 1-bit units.
PRSCM7
PRSCM
PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0
After reset: 00H
R/W
Address: FFFFF8B1H
Cautions 1. Do not change the value of the PRSCM register during transmission/reception.
2. Set the PRSCM register before setting the CE bit of the PRSM register to 1.
3. Set the PRSM and PRSCM registers in accordance with the main clock frequency to be
used, so that the frequency of fBRG is 32.768 kHz.
6.5.2
Generation of clock
(1) Count clock of watch timer
The clock (fBRG) input to the watch timer can be corrected to 32.768 kHz or equivalent frequency.
The relationship between the main clock oscillation frequency (fX), the set value of input clock selection bit
BGCSn (m), the set value of the PRCSM register (N), and the output clock (fBRG) is as follows:
Example: Where fX = 4.00 MHz, m = 0 (BGCS1 = BGCS = 0), N = 3DH, fBRG = 32.768 kHz
fBRG = fX/(2
m
× N × 2)
Remark
fBRG: Count clock
N:
Value of compare register in prescaler 3 (1 to FFH)
N = 256 if the value of the compare register is “00H”.
(2) Interval timer
This timer generates a baud rate interrupt request (INTBRG) at preset time intervals.
The interval time can be set by using the BGCS1 and BGCS0 bits of the prescaler mode register (PRSM) and
the prescaler compare register (PRSCM).
The interval time can be calculated by the following expression.
Interval time = fX/(2
m
× N)