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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18LF8490-I/PT |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 251/314闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 8KX16 80TQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 119 |
| 绯诲垪锛� | PIC® 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 40MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝HLVD锛孡CD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 66 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 768 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 12x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 鍖呰锛� | 鎵樼洡(p谩n) |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 647 (CN2011-ZH PDF) |
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RL78/G13
CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00
362
Sep 22, 2011
6.5 Operation Timing of Counter
6.5.1 Count clock (fTCLK)
The count clock (fTCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register
mn (TMRmn). .
Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits
Valid edge of input signal input from the TImn pin
Because the timer array unit is designed to operate in synchronization with fCLKTCLK) are
shown below.
(1) When operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0)
The count clock (fTCLK) is between fCLK to fCLK /2
15 by setting of timer clock select register m (TPSm). When a
divided fCLK is selected, however, the count clock is not a signal which is simply divided fCLK by 2
m, but a signal
which becomes high level for one period of fCLK from its rising edge (m = 1 to 15).
Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with fCLK. But, this is described as 鈥渃ounting at rising edge of the count clock鈥�, as a
matter of convenience.
Figure 6-21. Timing of fCLK and count clock (fTCLK) (When CCSmn = 0)
Remarks 1.
: Rising edge of the count clock
: Synchronization, increment/decrement of counter
2.
fCLK: CPU/peripheral hardware clock
fCLK
fTCLK
( = fMCK
= CKmn)
fCLK/2
fCLK/4
fCLK/8
fCLK/16
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| PIC18LF8621-I/PT | IC PIC MCU FLASH 32KX16 80TQFP |
| PIC18LF8622-I/PT | IC PIC MCU FLASH 32KX16 80TQFP |
| PIC18LF8627-I/PT | IC PIC MCU FLASH 48KX16 80TQFP |
| PIC18LF8680-I/PT | IC PIC MCU FLASH 32KX16 80TQFP |
| PIC18LF8720-I/PT | IC MCU FLASH 64KX16 LV 80-TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PIC18LF8490T-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16kBF 768RM 66 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18LF8493-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 192 Segmnt LCD DRVR 12B ADC 16KB 768BRAM RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18LF8493T-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 192 Segmnt LCD DRVR 12B ADC 16KB 768BRAM RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18LF8520-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 2048 RAM 68I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC18LF8520-I/PTG | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 2048 RAM 68I/O Lead Free Package RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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