
2005 Microchip Technology Inc.
DS39612B-page 163
PIC18F6525/6621/8525/8621
FIGURE 17-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
17.4.4
HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the P1A pin, while the complementary
PWM output signal is output on the P1B pin
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
on dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 17-4:
HALF-BRIDGE PWM
OUTPUT
0
Period
00
10
01
11
SIGNAL
PR2 + 1
CCP1CON
<7:6>
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1)
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note
1:
Period
Duty Cycle
td
(1)
P1A(2)
P1B(2)
td = Dead Band Delay
Period
(1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.