參數(shù)資料
型號： PIC18LF65K80-I/MR
廠商： Microchip Technology
文件頁數(shù)： 315/351頁
文件大?。?/td> 0K
描述： MCU PIC ECAN 32KB FLASH 64QFN
產(chǎn)品培訓(xùn)模塊： 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 40
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： ECAN，I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 3.6K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 管件
PIC18F66K80 FAMILY
DS39977F-page 66
2010-2012 Microchip Technology Inc.
4.1.3
CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable. The HF-
INTOSC and MF-INTOSC are termed as INTOSC in
this chapter.
Three bits indicate the current clock source and its
status, as shown in Table 4-2. The three bits are:
OSTS (OSCCON<3>)
HFIOFS (OSCCON<2>)
SOSCRUN (OSCCON2<6>)
When the OSTS bit is set, the primary clock is providing
the device clock. When the HFIOFS or MFIOFS bit is
set, the INTOSC output is providing a stable clock
source to a divider that actually drives the device clock.
When the SOSCRUN bit is set, the SOSC oscillator is
providing the clock. If none of these bits are set, either
the LF-INTOSC clock source is clocking the device or
the INTOSC source is not yet stable.
If the internal oscillator block is configured as the
primary clock source by the FOSC<3:0> Configuration
bits (CONFIG1H<3:0>). Then, the OSTS and HFIOFS
or MFIOFS bits can be set when in PRI_RUN or
PRI_IDLE mode. This indicates that the primary clock
(INTOSC output) is generating a stable output. Enter-
ing another INTOSC power-managed mode at the
same frequency would clear the OSTS bit.
4.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP
instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
4.2
Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled. (For details, see Section 28.4 “Two-Speed
.) In this mode, the OSTS bit is set. The
HFIOFS or MFIOFS bit may be set if the internal
oscillator block is the primary clock source. (See
.)
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock-switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the SOSC oscillator. This enables lower
power consumption while retaining a high-accuracy
clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
SOSC oscillator (see Figure 4-1), the primary oscillator
is shut down, the SOSCRUN bit (OSCCON2<6>) is set
and the OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the SOSC oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
SOSCRUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCSx bits are not affected by the wake-up and the
SOSC oscillator continues to run.
TABLE 4-2:
SYSTEM CLOCK INDICATOR
Main Clock Source
OSTS
HFIOFSor
MFIOFS
SOSCRUN
Primary Oscillator
10
0
INTOSC (HF-INTOSC
or MF-INTOSC)
01
0
Secondary Oscillator
00
1
MF-INTOSC or
HF-INTOSC as Primary
Clock Source
11
0
LF-INTOSC is
Running or INTOSC is
Not Yet Stable
00
0
Note 1:
Caution should be used when modifying
a single IRCF bit. At a lower VDD, it is
possible to select a higher clock speed
than is supportable by that VDD. Improper
device operation may result if the VDD/
FOSC specifications are violated.
2:
Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
Note:
The SOSC oscillator can be enabled by
setting the SOSCGO bit (OSCCON2<3>).
If this bit is set, the clock switch to the
SEC_RUN mode can switch immediately
once SCS<1:0> are set to ‘01’.
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