PIC18F66K80 FAMILY
DS39977F-page 84
2010-2012 Microchip Technology Inc.
5.6.2
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (Parameter
33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
5.6.3
PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
5.6.4
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1.
After the POR pulse has cleared, PWRT
time-out is invoked (if enabled).
2.
Then, the OST is activated.
The total time-out will vary based on oscillator configu-
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures
5-3 throug
h 5-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(
Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 5-2:
TIME-OUT IN VARIOUS SITUATIONS
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
Oscillator
Configuration
Power-up and Brown-out
Exit from
Power-Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2) HS, XT, LP
1024 TOSC
EC, ECIO
——
RC, RCIO
——
INTIO1, INTIO2
——
Note 1:
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2:
2 ms is the nominal time required for the PLL to lock.
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET