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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18LF45K80-I/ML
寤犲晢锛� Microchip Technology
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PIC18F66K80 FAMILY
DS39977F-page 296
2010-2012 Microchip Technology Inc.
21.4
I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support), and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
Serial Clock (SCL) 鈥� RC3/REFO/SCL/SCK
Serial Data (SDA) 鈥� RC4/SDA/SDI
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 21-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
21.4.1
REGISTERS
The MSSP module has seven registers for I2C
operation. These are:
MSSP Control Register 1 (SSPCON1)
MSSP Control Register 2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer Register
(SSPBUF)
MSSP Shift Register (SSPSR) 鈥� Not directly
accessible
MSSP Address Register (SSPADD)
I2C Slave Address Mask Register (SSPMSK)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD contains the slave device address when the
MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, all eight bits of
SSPADD act as the Baud Rate Generator reload value.
SSPMSK holds the slave address mask value when
the module is configured for 7-Bit Address Masking
mode. While it is a separate register, it shares the same
SFR address as SSPADD; it is only accessible when
the SSPM<3:0> bits are specifically set to permit
access.
Additional
details
are
provided
in
.
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During
transmission,
the
SSPBUF
is
not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
Read
Write
SSPSR reg
Match Detect
SSPADD reg
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
Shift
Clock
MSb
LSb
Note:
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
SCL
SDA
Start and
Stop bit Detect
Address Mask
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