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參數資料
| 型號： | PIC18LF43K22-I/P |
| 廠商： | Microchip Technology |
| 文件頁數： | 51/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU 8KB FLASH 40PDIP |
| 產品培訓模塊： | 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 10 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 64MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，HLVD，POR，PWM，WDT |
| 輸入/輸出數： | 35 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數據轉換器： | A/D 30x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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2010-2012 Microchip Technology Inc.
DS41412F-page 55
PIC18(L)F2X/4XK22
3.6
Selective Peripheral Module
Control
Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus, con-
sume power. There may be cases where the applica-
tion needs what IDLE mode does not provide: the
allocation of power resources to the CPU processing
with minimal power consumption from the peripherals.
PIC18(L)F2X/4XK22
family
devices
address
this
requirement by allowing peripheral modules to be
selectively disabled, reducing or eliminating their
power consumption. This can be done with control bits
in the Peripheral Module Disable (PMD) registers.
These bits generically named XXXMD are located in
control registers PMD0, PMD1 or PMD2.
Setting the PMD bit for a module disables all clock
sources
to
that
module,
reducing
its
power
consumption to an absolute minimum. In this state,
power to the control and status registers associated
with the peripheral is removed. Writes to these
registers have no effect and read values are invalid.
Clearing a set PMD bit restores power to the
associated control and status registers, thereby setting
those registers to their default values.
3.7
Register Definitions: Peripheral Module Disable
REGISTER 3-1:
PMD0: PERIPHERAL MODULE DISABLE REGISTER 0
R/W-0
UART2MD
UART1MD
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
UART2MD: UART2 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
bit 6
UART1MD: UART1 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
bit 5
TMR6MD: Timer6 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
bit 4
TMR5MD: Timer5 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
bit 3
TMR4MD: Timer4 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
bit 2
TMR3MD: Timer3 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
bit 1
TMR2MD: Timer2 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
bit 0
TMR1MD: Timer1 Peripheral Module Disable Control bit
1
= Module is disabled, Clock Source is disconnected, module does not draw digital power
0
= Module is enabled, Clock Source is connected, module draws digital power
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