TR MCLR Rise Time to Enter" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18LF26J50-I/SS
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 24/32闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC PIC MCU FLASH 64K 2V 28-SSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧栧寘瑁濓細 47
绯诲垪锛� PIC® XLP™ 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 48MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孌MA锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 16
绋嬪簭瀛樺劜鍣ㄥ閲忥細 64KB锛�32K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 3.8K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 10x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 28-SSOP锛�0.209"锛�5.30mm 瀵級
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 657 (CN2011-ZH PDF)
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 30
2009 Microchip Technology Inc.
P1
TR
MCLR Rise Time to Enter Program/Verify
mode
鈥�1.0
渭s
P2
TPGC
Serial Clock (PGC) Period
100
鈥�
ns
P2A
TPGCL
Serial Clock (PGC) Low Time
50
鈥�
ns
P2B
TPGCH
Serial Clock (PGC) High Time
50
鈥�
ns
P3
TSET1
Input Data Setup Time to Serial Clock
鈫�
20
鈥�
ns
P4
THLD1
Input Data Hold Time from PGC
鈫�
20
鈥�
ns
P5
TDLY1
Delay Between 4-Bit Command and
Command Operand
50
鈥�
ns
P5A
TDLY1A
Delay Between 4-Bit Command Operand and
Next 4-Bit Command
50
鈥�
ns
P6
TDLY2
Delay Between Last PGC
鈫� of Command Byte
to First PGC
鈫� of Read of Data Word
20
鈥�
ns
P9
TDLY5
Delay to allow Block Programming to Occur
3.4
鈥�
ms
PIC18F2XJ10/PIC18F4XJ10
1.2
鈥�
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ5X/PIC18F4XJ5X
P10
TDLY6
Delay to allow Row Erase to Occur
49
鈥�
ms
PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
54
鈥�
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P11
TDLY7
Delay to allow Bulk Erase to Occur
475
鈥�
ms
PIC18F2XJ10/PIC18F4XJ10/
PIC18F2XJ13/PIC18F4XJ13/
PIC18F2XJ53/PIC18F4XJ53
524
鈥�
ms
PIC18F2XJ11/PIC18F4XJ11/
PIC18F2XJ50/PIC18F4XJ50
P12
THLD2
Input Data Hold Time from MCLR
鈫�
400
鈥�
渭s
P13
TSET2VDD
鈫� Setup Time to MCLR 鈫�
100
鈥�
ns
P14
TVALID
Data Out Valid from PGC
鈫�
25
鈥�
ns
P16
TDLY8
Delay Between Last PGC
鈫� and MCLR 鈫�
20
鈥�
ns
P17
THLD3MCLR
鈫� to VDD 鈫�
3鈥�
渭s
P19
TKEY1
Delay from First MCLR
鈫� to First PGC 鈫� for
Key Sequence on PGD
4鈥�
ms
P20
TKEY2
Delay from Last PGC
鈫� for Key Sequence on
PGD to Second MCLR
鈫�
50
鈥�
ns
6.0
AC/DC CHARACTERISTICS TIMING REQUIREMENTS
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25
掳C is recommended
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
Note 1:
External power must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See
Section 2.1.1 鈥淧IC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator鈥� for
more information.
2:
VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within 卤0.3V
of VDD and VSS, respectively.
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