參數(shù)資料
型號: PIC18LF2450T-I/SO
廠商: Microchip Technology
文件頁數(shù): 73/143頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 28SOIC
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 33
3.0
POWER-MANAGED MODES
PIC18F2450/4450 devices offer a total of seven
operating
modes
for
more
efficient
power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
Run modes
Idle modes
Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator); the
Sleep mode does not use a clock source.
The power-managed modes include several power-
saving
features
offered
on
previous
PICmicro
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PICmicro
devices, where all device clocks are stopped.
3.1
Selecting Power-Managed Modes
Selecting
a
power-managed
mode
requires
two
decisions: if the CPU is to be clocked or not and the
selection
of
a
clock
source.
The
IDLEN
bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 3-1.
3.1.1
CLOCK SOURCES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
The primary clock, as defined by the
FOSC3:FOSC0 Configuration bits
The secondary clock (the Timer1 oscillator)
The internal oscillator (for RC modes)
3.1.2
ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins
by
loading
the
OSCCON
register.
The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP
instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
TABLE 3-1:
POWER-MANAGED MODES
Mode
OSCCON Bits
Module Clocking
Available Clock and Oscillator Source
IDLEN(1)
SCS1:SCS0
CPU
Peripherals
Sleep
0
N/A
Off
None – all clocks are disabled
PRI_RUN
N/A
00
Clocked
Primary – all oscillator modes.
This is the normal full power execution mode.
SEC_RUN
N/A
01
Clocked
Secondary – Timer1 oscillator
RC_RUN
N/A
1x
Clocked
Internal oscillator(2)
PRI_IDLE
100
Off
Clocked
Primary – all oscillator modes
SEC_IDLE
101
Off
Clocked
Secondary – Timer1 oscillator
RC_IDLE
11x
Off
Clocked
Internal oscillator(2)
Note 1:
IDLEN reflects its value when the SLEEP instruction is executed.
2:
Clock is INTRC source.
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