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PIC18F2423/2523/4423/4523
DS39755C-page 32
2009 Microchip Technology Inc.
2.4
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS<2:0> bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT<2:0> bits do not
need to be adjusted as the ADCS<2:0> bits adjust the
TAD time for the new clock speed. After entering the
mode, an A/D acquisition or conversion may be started.
Once started, the device should continue to be clocked
by the same clock source until the conversion has been
completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If bits, ACQT<2:0>, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN bit
(OSCCON<7>) must have already been cleared prior
to starting the conversion.
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
3: The
PBADEN
bit
in
Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by controlling
how the PCFG<3:0> bits in ADCON1 are
reset.
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