
159
9157C–AVR–03/12
Atmel ATtiny88 Automotive
15.9.7
TWHSR – TWI High Speed Register
Bits 7..1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 0 – TWHS: TWI High Speed Enable
TWI High Speed mode is enabled by writing this bit to one. In this mode the undivided system
The TWI High Speed mode requires that the high-speed clock, clk
TWIHS, is exactly two times
higher than the I/O clock frequency, clk
I/O. This means the user must make sure the I/O clock
frequency clk
I/O is scaled down by a factor of 2. For example, if the internal 8 MHz oscillator has
been selected as source clock, the user must set the prescaler to scale the system clock (and,
hence, the I/O clock) down to 4 MHz. For more information about clock systems, see
“ClockBit
7
65
43
21
0
––
–
TWHS
TWHSR
Read/Write
RR
R
R/W
Initial Value
0