參數(shù)資料
型號(hào)： PIC18F97J60-I/PT
廠商： Microchip Technology
文件頁數(shù)： 4/8頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 64KX16 100TQFP
產(chǎn)品培訓(xùn)模塊： Embedded Ethernet
Asynchronous Stimulus
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 119
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 41.667MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 70
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 3808 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 645 (CN2011-ZH PDF)
配用： AC162064-ND - HEADER INTFC MPLABICD2 64/80/100
DM163024-ND - BOARD DEMO PICDEM.NET 2
AC164323-ND - MODULE SKT FOR 100TQFP
PIC18F97J60 FAMILY
DS80292D-page 4
2008 Microchip Technology Inc.
7.
Module: Ethernet (TX)
When configured for half duplex and a transmit
operation encounters unusual collision timing,
there is a small chance that the Ethernet transmit
engine will internally deadlock. The PHY will stop
transmitting the packet and normal RX operations
will
continue.
However,
the
TXRTS
bit
(ECON1<3>) will stay set indefinitely. The TXIF
(EIR<3>) and TXERIF (EIR<1>) bits will not
become set.
This deadlock condition applies only to half-duplex
operation and is most readily observable when the
network has a duplex mismatch (i.e., PIC18F97J60
family device is configured for half duplex and the
remote node is configured for full duplex). In most
cases, high network utilization is needed to observe
the issue.
Work around
To prevent most transmit deadlock conditions,
issue a TX Logic Reset prior to transmitting each
packet:
1. Set TXRST (ECON1<7>)
2. Clear TXRST
3. Wait 1.6
μs or longer
4. Set TXRTS to start the transmission.
Issuing a TX Logic Reset may cause the Ethernet
transmit error interrupt to occur and the associated
TXERIF bit to become set, which can be ignored.
To detect and recover from any possible deadlock
conditions, applications should implement a timer to
poll the TXRTS bit. If the Ethernet hardware enters
the deadlock state and fails to clear this bit by the
time the timer expires, software should manually
clear the TXRTS bit, issue a TX Logic Reset and
then set the TXRTS bit to retry transmission. The
timer should be cleared and restarted whenever the
application sets TXRTS. The timer expiration time
should be chosen to allow adequate time for
ordinary
packets
to
finish
transmitting,
after
accounting for possible delays due to the medium
being occupied by other nodes. For example, a
time-out value of 3 ms is suitable since it will allow a
maximum length 1518-byte packet to be transmit-
ted at 10Base-T speeds while giving reasonable
margin to account for potential collisions.
Date Codes that pertain to this issue:
All engineering and production devices.
8.
Module: Ethernet (DMA)
When the DMA is configured to compute an IP
checksum, there is a small chance that an incom-
ing packet receive event will cause the DMA to
internally deadlock. In these cases, the DMAST bit
(ECON1<5>) stays set indefinitely, and the DMA
done interrupt never occurs.
Work around
Perform checksum calculations in software. Use
the DMA only for copy operations.
Date Codes that pertain to this issue:
All engineering and production devices.
9.
Module: I/O (PORTJ)
The weak internal pull-up resistors on pins RJ4
and RJ5 cannot be enabled on the PIC18F86J60,
PIC18F86J65 and PIC18F87J60 devices. Setting
the RJPU bit (PORTA<7>) has no effect on the I/O
pin state.
Work around
Install external pull-up resistors on RJ4 and RJ5.
Alternatively, use any of the PORTB, PORTD or
PORTE pins which all have weak internal pull ups.
Date Codes that pertain to this issue:
All engineering and production devices.
Note:
This issue is only applicable to the
80-pin device.
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