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      參數(shù)資料
      型號(hào): PIC18F87J90-I/PT
      廠(chǎng)商: Microchip Technology
      文件頁(yè)數(shù): 32/59頁(yè)
      文件大小: 0K
      描述: IC PIC MCU FLASH 128KB 80-TQFP
      產(chǎn)品培訓(xùn)模塊: PIC18 J Series MCU Overview
      8-bit PIC® Microcontroller Portfolio
      標(biāo)準(zhǔn)包裝: 119
      系列: PIC® 18F
      核心處理器: PIC
      芯體尺寸: 8-位
      速度: 48MHz
      連通性: I²C,SPI,UART/USART
      外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,LVD,POR,PWM,WDT
      輸入/輸出數(shù): 67
      程序存儲(chǔ)器容量: 128KB(64K x 16)
      程序存儲(chǔ)器類(lèi)型: 閃存
      RAM 容量: 3.8K x 8
      電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
      數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
      振蕩器型: 內(nèi)部
      工作溫度: -40°C ~ 85°C
      封裝/外殼: 80-TQFP
      包裝: 托盤(pán)
      產(chǎn)品目錄頁(yè)面: 644 (CN2011-ZH PDF)
      配用: AC162079-ND - HEADER MPLAB ICD2 18F85J90 64/80
      AC164323-ND - MODULE SKT FOR 100TQFP
      PIC18F87J90 FAMILY
      DS39933D-page 38
      2010 Microchip Technology Inc.
      3.3.1
      CLOCK SOURCE SELECTION
      The
      System
      Clock
      Select
      bits,
      SCS<1:0>
      (OSCCON<1:0>), select the clock source. The avail-
      able clock sources are the primary clock defined by the
      FOSC<2:0> Configuration bits, the secondary clock
      (Timer1 oscillator) and the internal oscillator. The clock
      source changes after one or more of the bits is written
      to, following a brief clock transition interval.
      The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
      bits indicate which clock source is currently providing
      the device clock. The OSTS bit indicates that the
      Oscillator Start-up Timer (OST) has timed out and the
      primary clock is providing the device clock in Primary
      Clock modes. The T1RUN bit indicates when the
      Timer1 oscillator is providing the device clock in
      Secondary Clock modes. In power-managed modes,
      only one of these bits will be set at any time. If neither
      of these bits is set, the INTRC is providing the clock, or
      the internal oscillator has just started and is not yet
      stable.
      The IDLEN bit determines if the device goes into Sleep
      mode or one of the Idle modes when the SLEEP
      instruction is executed.
      The use of the flag and control bits in the OSCCON
      register is discussed in more detail in Section 4.0
      3.3.1.1
      System Clock Selection and Device
      Resets
      Since the SCS bits are cleared on all forms of Reset,
      this means the primary oscillator defined by the
      FOSC<2:0> Configuration bits is used as the primary
      clock source on device Resets. This could either be the
      internal oscillator block by itself or one of the other
      primary clock source (HS, EC, HSPLL, ECPLL1/2 or
      INTPLL1/2).
      In those cases when the internal oscillator block, with-
      out PLL, is the default clock on Reset, the Fast RC
      oscillator (INTOSC) will be used as the device clock
      source. It will initially start at 1 MHz; the postscaler
      selection that corresponds to the Reset value of the
      IRCF<2:0> bits (‘100’).
      Regardless of which primary oscillator is selected,
      INTRC will always be enabled on device power-up. It
      serves as the clock source until the device has loaded
      its configuration values from memory. It is at this point
      that the FOSC Configuration bits are read and the
      oscillator selection of the operational mode is made.
      Note that either the primary clock source, or the internal
      oscillator, will have two bit setting options for the possible
      values of the SCS<1:0> bits at any given time.
      3.3.2
      OSCILLATOR TRANSITIONS
      PIC18F87J90 family devices contain circuitry to
      prevent clock “glitches” when switching between clock
      sources. A short pause in the device clock occurs dur-
      ing the clock switch. The length of this pause is the sum
      of two cycles of the old clock source and three to four
      cycles of the new clock source. This formula assumes
      that the new clock source is stable.
      Clock transitions are discussed in greater detail in
      Note 1: The Timer1 oscillator must be enabled to
      select the secondary clock source. The
      Timer1 oscillator is enabled by setting the
      T1OSCEN bit in the Timer1 Control regis-
      ter (T1CON<3>). If the Timer1 oscillator is
      not enabled, then any attempt to select a
      secondary clock source when executing a
      SLEEP
      instruction will be ignored.
      2: It is recommended that the Timer1
      oscillator be operating and stable before
      executing the SLEEP instruction or a very
      long delay may occur while the Timer1
      oscillator starts.
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