SLOW RISE TIME (MCLR TIED TO V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18F8720-I/PT
寤犲晢锛� Microchip Technology
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PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 38
2004 Microchip Technology Inc.
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD VIA 1 k
RESISTOR)
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED
(MCLR TIED TO VDD VIA 1 k
RESISTOR)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note:
TOST = 1024 clock cycles.
TPLL
鈮� 2 ms max. First three stages of the PWRT timer.
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