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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC18F85K90-I/PTRSL |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 101/110闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU PIC 32K FLASH XLP 80TQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 119 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 64MHz |
| 閫ｉ€氭€э細 | I²C锛孡IN锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孡CD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 69 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�16K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶у皬锛� | 1K x 8 |
| RAM 瀹归噺锛� | 2K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 24x12b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 鍖呰锛� | 鎵樼洡 |
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2010 Microchip Technology Inc.
Preliminary
DS39964B-page 547
PIC18F47J53 FAMILY
TABLE 31-25: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock High Time
100 kHz mode
4.0
鈥�
s
400 kHz mode
0.6
鈥�
s
MSSP modules
1.5 TCY
鈥�
101
TLOW
Clock Low Time
100 kHz mode
4.7
鈥�
s
400 kHz mode
1.3
鈥�
s
MSSP modules
1.5 TCY
鈥�
102
TR
SDAx and SCLx Rise Time 100 kHz mode
鈥�
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
CB is specified to be from
10 to 400 pF
103
TF
SDAx and SCLx Fall Time 100 kHz mode
鈥�
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
CB is specified to be from
10 to 400 pF
90
TSU:STA
Start Condition Setup Time 100 kHz mode
4.7
鈥�
s
Only relevant for Repeated
Start condition
400 kHz mode
0.6
鈥�
s
91
THD:STA
Start Condition Hold Time 100 kHz mode
4.0
鈥�
s
After this period, the first clock
pulse is generated
400 kHz mode
0.6
鈥�
s
106
THD:DAT
Data Input Hold Time
100 kHz mode
0
鈥�
ns
400 kHz mode
0
0.9
s
107
TSU:DAT
Data Input Setup Time
100 kHz mode
250
鈥�
ns
(Note 2)
400 kHz mode
100
鈥�
ns
92
TSU:STO
Stop Condition Setup Time 100 kHz mode
4.7
鈥�
s
400 kHz mode
0.6
鈥�
s
109
TAA
Output Valid from Clock
100 kHz mode
鈥�
3500
ns
(Note 1)
400 kHz mode
鈥�
ns
110
TBUF
Bus Free Time
100 kHz mode
4.7
鈥�
s
Time the bus must be free
before a new transmission can
start
400 kHz mode
1.3
鈥�
s
D102
CB
Bus Capacitive Loading
鈥�
400
pF
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
2:
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT
250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR
max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is
released.
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