參數(shù)資料
型號(hào)： PIC18F67J90-I/PT
廠商： Microchip Technology
文件頁數(shù)： 40/59頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 128KB 64-TQFP
產(chǎn)品培訓(xùn)模塊： PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 160
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LCD，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 51
程序存儲(chǔ)器容量： 128KB（64K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 644 (CN2011-ZH PDF)
配用： AC162079-ND - HEADER MPLAB ICD2 18F85J90 64/80
AC164328-ND - MODULE SKT FOR 80TQFP
2010 Microchip Technology Inc.
DS39933D-page 45
PIC18F87J90 FAMILY
4.0
POWER-MANAGED MODES
The PIC18F87J90 family devices provide the ability to
manage power consumption by simply managing clock-
ing to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
Run mode
Idle mode
Sleep mode
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
The
power-managed
modes
include
several
power-saving features offered on previous PIC
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS<1:0> bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
4.1.1
CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
the primary clock, as defined by the FOSC<2:0>
Configuration bits
the secondary clock (Timer1 oscillator)
the internal oscillator
4.1.2
ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP
instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
TABLE 4-1:
POWER-MANAGED MODES
Mode
OSCCON Bits
Module Clocking
Available Clock and Oscillator Source
IDLEN<7>(1)
SCS<1:0>
CPU
Peripherals
Sleep
0
N/A
Off
None – All clocks are disabled
PRI_RUN
N/A
10
Clocked
Primary – HS, EC, HSPLL, ECPLL;
this is the normal full-power execution mode
SEC_RUN
N/A
01
Clocked
Secondary – Timer1 Oscillator
RC_RUN
N/A
11
Clocked
Internal Oscillator
PRI_IDLE
110
Off
Clocked
Primary – HS, EC, HSPLL, ECPLL
SEC_IDLE
101
Off
Clocked
Secondary – Timer1 Oscillator
RC_IDLE
111
Off
Clocked
Internal Oscillator
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
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