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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC18F67J10-I/PT |
| 寤�(ch菐ng)鍟嗭細 | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 25/44闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU FLASH 64KX16 64TQFP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 160 |
| 绯诲垪锛� | PIC® 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 40MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 50 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 128KB锛�64K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 3.8K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 11x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 64-TQFP |
| 鍖呰锛� | 鎵樼洡(p谩n) |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 644 (CN2011-ZH PDF) |
| 閰嶇敤锛� | MA180015-ND - MODULE PLUG-IN 18F87J10 FOR HPC AC162062-ND - HEADER INTRFC MPLAB ICD2 64/80P AC164327-ND - MODULE SKT FOR 64TQFP |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)鐣�(d膩ng)鍓嶇25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)
2009 Microchip Technology Inc.
DS39663F-page 29
PIC18F87J10 FAMILY
2.4
Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 24.3 鈥淥n-Chip Voltage
Regulator鈥� for details on connecting and using the
on-chip regulator.
When the regulator is enabled, a low-ESR (<5)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10
渭F connected to ground. The
type can be ceramic or tantalum. A suitable example is
the Murata GRM21BF50J106ZE01 (10
渭F, 6.3V) or
equivalent. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 27.0 鈥淓lectrical
Characteristics鈥� for additional information.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 27.0 鈥淓lectrical Characteristics鈥� for
information on VDD and VDDCORE.
Note that the 鈥淟F鈥� versions of some low pin count
PIC18FJ parts (e.g., the PIC18LF45J10) do not have
the ENVREG pin. These devices are provided with the
voltage regulator permanently disabled; they must
always be provided with a supply voltage on the
VDDCORE pin.
FIGURE 2-3:
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
2.5
ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming (ICSP) and debugging purposes. It is
recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100.
Pull-up resistors, series diodes and capacitors on the
PGC and PGD pins are not recommended as they will
interfere
with
the
programmer/debugger
com-
munications to the device. If such discrete components
are an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits and pin input voltage high (VIH)
and input low (VIL) requirements.
For device emulation, ensure that the 鈥淐ommunication
Channel Select鈥� (i.e., PGC/PGD pins) programmed
into the device matches the physical connections for
the ICSP to the MPLAB ICD 2, MPLAB ICD 3 or
REAL ICE emulator.
For more information on the ICD 2, ICD 3 and REAL ICE
emulator connection requirements, refer to the following
documents that are available on the Microchip web site.
鈥淢PLAB ICD 2 In-Circuit Debugger User鈥檚
Guide鈥� (DS51331)
鈥淯sing MPLAB ICD 2鈥� (poster) (DS51265)
鈥淢PLAB ICD 2 Design Advisory鈥� (DS51566)
鈥淯sing MPLAB ICD 3鈥� (poster) (DS51765)
鈥淢PLAB ICD 3 Design Advisory鈥� (DS51764)
鈥淢PLAB REAL ICE In-Circuit Emulator User鈥檚
Guide鈥� (DS51616)
鈥淯sing MPLAB REAL ICE In-Circuit Emulator鈥�
(poster) (DS51749)
10
1
0.1
0.01
0.001
0.01
0.1
1
10
100
1000 10,000
Frequency (MHz)
ES
R
(
惟
)
Note:
Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25掳C, 0V DC bias.
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