參數(shù)資料
型號(hào): PIC18F6720T-E/PT
廠商: Microchip Technology
文件頁數(shù): 163/165頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KX16 64TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 3.75K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
配用: MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
2004 Microchip Technology Inc.
DS39609B-page 95
PIC18F6520/8520/6620/8620/6720/8720
9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2 and PIE3).
When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must
be set to enable any of these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
ADIE
RC1IE
TX1IE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1
= Enables the PSP read/write interrupt
0
= Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1
= Enables the A/D interrupt
0
= Disables the A/D interrupt
bit 5
RC1IE: USART1 Receive Interrupt Enable bit
1
= Enables the USART1 receive interrupt
0
= Disables the USART1 receive interrupt
bit 4
TX1IE: USART1 Transmit Interrupt Enable bit
1
= Enables the USART1 transmit interrupt
0
= Disables the USART1 transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1
= Enables the MSSP interrupt
0
= Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1
= Enables the CCP1 interrupt
0
= Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1
= Enables the TMR2 to PR2 match interrupt
0
= Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1
= Enables the TMR1 overflow interrupt
0
= Disables the TMR1 overflow interrupt
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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