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參數資料
| 型號： | PIC18F66J15-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數： | 31/44頁 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 48KX16 64TQFP |
| 產品培訓模塊： | Asynchronous Stimulus PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 160 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數： | 50 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數據轉換器： | A/D 11x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 644 (CN2011-ZH PDF) |
| 配用： | MA180015-ND - MODULE PLUG-IN 18F87J10 FOR HPC AC162062-ND - HEADER INTRFC MPLAB ICD2 64/80P AC164327-ND - MODULE SKT FOR 64TQFP |
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2009 Microchip Technology Inc.
DS39663F-page 35
PIC18F87J10 FAMILY
3.6.1
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 3-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS<1:0>, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC<2:0> Configura-
tion bits), the secondary clock (Timer1 oscillator) and
the internal oscillator. The clock source changes after
one or more of the bits are written to, following a brief
clock transition interval.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these bits will be set at any time. If neither
of these bits are set, the INTRC is providing the clock,
or the internal oscillator has just started and is not yet
stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
3.6.1.1
System Clock Selection and the
FOSC2 Configuration Bit
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC<1:0> (that is, one of the HC
or EC modes) is used as the primary clock source on
device Resets.
The default clock configuration on Reset can be
changed with the FOSC2 Configuration bit. The effect of
this bit is to set the clock source selected when
SCS<1:0> = 00. When FOSC2 = 1 (default), the
oscillator source defined by FOSC<1:0> is selected
whenever SCS<1:0> = 00. When FOSC2 = 0, the
INTRC oscillator is selected whenever SCS<1:2> = 00.
Because the SCS bits are cleared on Reset, the FOSC2
setting also changes the default oscillator mode on
Reset.
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It will serve as the
clock source until the device has loaded its configura-
tion values from memory. It is at this point that the
FOSC Configuration bits are read and the oscillator
selection of the operational mode is made.
Note that either the primary clock or the internal
oscillator will have two bit setting options, at any given
time, depending on the setting of FOSC2.
3.6.2
OSCILLATOR TRANSITIONS
PIC18F87J10 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
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