參數(shù)資料
型號(hào): PIC18F66J11-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 3/107頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32KX16 64TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3930 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 644 (CN2011-ZH PDF)
配用: AC162091-ND - HEADER MPLAB ICD2 18F87J11 64/80
MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
AC164327-ND - MODULE SKT FOR 64TQFP
PIC18F87J11 FAMILY
DS39778E-page 100
2007-2012 Microchip Technology Inc.
7.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased.
TBLPTR<9:0> are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
Load Table Pointer register with address of row
being erased.
2.
Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3.
Disable interrupts.
4.
Write H'55' to EECON2.
5.
Write H'AA' to EECON2.
6.
Set the WR bit. This will begin the row erase
cycle.
7.
The CPU will stall for duration of the erase for
TIW (see Parameter D133A).
8.
Re-enable interrupts.
EXAMPLE 7-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
CODE_ADDR_UPPER
; load TBLPTR with the base
MOVWF
TBLPTRU
; address of the memory block
MOVLW
CODE_ADDR_HIGH
MOVWF
TBLPTRH
MOVLW
CODE_ADDR_LOW
MOVWF
TBLPTRL
ERASE_ROW
BSF
EECON1, WREN
; enable write to memory
BSF
EECON1, FREE
; enable Row Erase operation
BCF
INTCON, GIE
; disable interrupts
Required
MOVLW
H'55'
Sequence
MOVWF
EECON2
; write H'55'
MOVLW
H'AA'
MOVWF
EECON2
; write H'AA'
BSF
EECON1, WR
; start erase (CPU stall)
BSF
INTCON, GIE
; re-enable interrupts
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