參數(shù)資料
型號： PIC18F46J50T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 25/164頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 64KB 44-TQFP
產(chǎn)品培訓模塊： PIC18 J Series MCU Overview
PIC18F MPLAB® Starter Kit
標準包裝： 1,200
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設備： 欠壓檢測/復位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 13x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 帶卷 (TR)
配用： AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
PIC18F46J50 FAMILY
DS39931D-page 120
2011 Microchip Technology Inc.
9.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
Note 1:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2:
User
software
should
ensure
the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh)
R/W-0
R-0
R/W-0
PMPIF(1)
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PMPIF:
Parallel Master Port Read/Write Interrupt Flag bit(1)
1
= A read or a write operation has taken place (must be cleared in software)
0
= No read or write has occurred
bit 6
ADIF:
A/D Converter Interrupt Flag bit
1
= An A/D conversion completed (must be cleared in software)
0
= The A/D conversion is not complete
bit 5
RC1IF:
EUSART1 Receive Interrupt Flag bit
1
= The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0
= The EUSART1 receive buffer is empty
bit 4
TX1IF:
EUSART1 Transmit Interrupt Flag bit
1
= The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0
= The EUSART1 transmit buffer is full
bit 3
SSP1IF:
Master Synchronous Serial Port 1 Interrupt Flag bit
1
= The transmission/reception is complete (must be cleared in software)
0
= Waiting to transmit/receive
bit 2
CCP1IF:
ECCP1 Interrupt Flag bit
Capture mode:
1
= A TMR1/TMR3 register capture occurred (must be cleared in software)
0
= No TMR1/TMR3 register capture occurred
Compare mode:
1
= A TMR1/TMR3 register compare match occurred (must be cleared in software)
0
= No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF:
TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match occurred (must be cleared in software)
0
= No TMR2 to PR2 match occurred
bit 0
TMR1IF:
TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
Note 1:
These bits are unimplemented on 28-pin devices.
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