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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4680-I/P
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 280/322闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU FLASH 32KX16 40DIP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫ｉ€氭€э細 CAN锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 64KB锛�32K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 3.25K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 11x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 40-DIP锛�0.600"锛�15.24mm锛�
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 646 (CN2011-ZH PDF)
閰嶇敤锛� I3-DB18F4680-ND - BOARD DAUGHTER ICEPIC3
DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
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PIC18F2585/2680/4585/4680
DS39625C-page 58
Preliminary
2007 Microchip Technology Inc.
B2CON(6)
2585 2680 4585 4680
0000 0000
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B1D7(6)
2585 2680 4585 4680
xxxx xxxx
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B1D6(6)
2585 2680 4585 4680
xxxx xxxx
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B1D5(6)
2585 2680 4585 4680
xxxx xxxx
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B1D4(6)
2585 2680 4585 4680
xxxx xxxx
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B1D3(6)
2585 2680 4585 4680
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B1D2(6)
2585 2680 4585 4680
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B1D1(6)
2585 2680 4585 4680
xxxx xxxx
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B1D0(6)
2585 2680 4585 4680
xxxx xxxx
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B1DLC(6)
2585 2680 4585 4680
-xxx xxxx
-uuu uuuu
B1EIDL(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1EIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1SIDL(6)
2585 2680 4585 4680
xxxx x-xx
uuuu u-uu
B1SIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1CON(6)
2585 2680 4585 4680
0000 0000
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B0D7(6)
2585 2680 4585 4680
xxxx xxxx
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B0D6(6)
2585 2680 4585 4680
xxxx xxxx
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B0D5(6)
2585 2680 4585 4680
xxxx xxxx
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B0D4(6)
2585 2680 4585 4680
xxxx xxxx
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B0D3(6)
2585 2680 4585 4680
xxxx xxxx
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B0D2(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D1(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D0(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0DLC(6)
2585 2680 4585 4680
-xxx xxxx
-uuu uuuu
B0EIDL(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0EIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0SIDL(6)
2585 2680 4585 4680
xxxx x-xx
uuuu u-uu
B0SIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0CON(6)
2585 2680 4585 4680
0000 0000
uuuu uuuu
TXBIE(6)
2585 2680 4585 4680
---0 00--
---u uu--
BIE0(6)
2585 2680 4585 4680
0000 0000
uuuu uuuu
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 鈥�0鈥�, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 4-3 for Reset value for specific condition.
5:
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read 鈥�0鈥�.
6:
This register reads all 鈥�0鈥檚 until the ECAN technology is set up in Mode 1 or Mode 2.
鐩搁棞(gu膩n)PDF璩囨枡
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